openpower/isa/pifixedstoreshift.mdwn

   1 <!-- This defines DRAFT instructions described in SV -->
   2
   3 <!-- This defines instructions that store from a register to RAM -->
   4 <!-- Effective Address is always RA, and the usual EA is stored late in RA -->
   5
   6 # Store Byte with Post-Update Indexed
   7
   8 X-Form
   9
  10 * stbupx RS,RA,RB
  11
  12 Pseudo-code:
  13
  14     EA <- (RA) + (RB)
  15     ea <- (RA)
  16     MEM(ea, 1) <- (RS)[XLEN-8:XLEN-1]
  17     RA <- EA
  18
  19 Description:
  20
  21     Let the effective address (EA) be the sum (RA)+ (RB).
  22
  23     (RS)[56:63] are stored into the byte in storage addressed
  24     by EA.
  25
  26     EA is placed into register RA.
  27
  28     If RA=0, the instruction form is invalid.
  29
  30 Special Registers Altered:
  31
  32     None
  33
  34 # Store Halfword with Post-Update Indexed
  35
  36 X-Form
  37
  38 * sthupx RS,RA,RB
  39
  40 Pseudo-code:
  41
  42     EA <- (RA) + (RB)
  43     ea <- (RA)
  44     MEM(ea, 2) <- (RS)[XLEN-16:XLEN-1]
  45     RA <- EA
  46
  47 Description:
  48
  49     Let the effective address (EA) be the sum (RA)+ (RB).
  50
  51     (RS)[56:63] are stored into the byte in storage addressed
  52     by EA.
  53
  54     EA is placed into register RA.
  55
  56     If RA=0, the instruction form is invalid
  57
  58 Special Registers Altered:
  59
  60     None
  61
  62 # Store Word with Post-Update Indexed
  63
  64 X-Form
  65
  66 * stwupx RS,RA,RB
  67
  68 Pseudo-code:
  69
  70     EA <- (RA) + (RB)
  71     ea <- (RA)
  72     MEM(ea, 4) <- (RS)[XLEN-32:XLEN-1]
  73     RA <- EA
  74
  75 Description:
  76
  77     Let the effective address (EA) be the sum (RA)+ (RB).
  78
  79     (RS)[32:63] are stored into the word in storage addressed
  80     by RA.
  81
  82     EA is placed into register RA.
  83
  84     If RA=0, the instruction form is invalid.
  85
  86 Special Registers Altered:
  87
  88     None
  89
  90 # Store Doubleword with Post-Update Indexed
  91
  92 X-Form
  93
  94 * stdupx RS,RA,RB
  95
  96 Pseudo-code:
  97
  98     EA <- (RA) + (RB)
  99     ea <- (RA)
 100     MEM(ea, 8) <- (RS)
 101     RA <- EA
 102
 103 Description:
 104
 105     Let the effective address (EA) be the sum (RA)+ (RB).
 106
 107     (RS) is stored into the doubleword in storage
 108     addressed by RA.
 109
 110     EA is placed into register RA.
 111
 112     If RA=0, the instruction form is invalid.
 113
 114 Special Registers Altered:
 115
 116     None
 117