1 <!-- This defines DRAFT instructions described in SV -->
3 <!-- This defines instructions that store from a register to RAM -->
4 <!-- Effective Address is always RA, and the usual EA is stored late in RA -->
6 # Store Byte with Post-Update Indexed
16 MEM(ea, 1) <- (RS)[XLEN-8:XLEN-1]
21 Let the effective address (EA) be the sum (RA)+ (RB).
23 (RS)[56:63] are stored into the byte in storage addressed
26 EA is placed into register RA.
28 If RA=0, the instruction form is invalid.
30 Special Registers Altered:
34 # Store Halfword with Post-Update Indexed
44 MEM(ea, 2) <- (RS)[XLEN-16:XLEN-1]
49 Let the effective address (EA) be the sum (RA)+ (RB).
51 (RS)[56:63] are stored into the byte in storage addressed
54 EA is placed into register RA.
56 If RA=0, the instruction form is invalid
58 Special Registers Altered:
62 # Store Word with Post-Update Indexed
72 MEM(ea, 4) <- (RS)[XLEN-32:XLEN-1]
77 Let the effective address (EA) be the sum (RA)+ (RB).
79 (RS)[32:63] are stored into the word in storage addressed
82 EA is placed into register RA.
84 If RA=0, the instruction form is invalid.
86 Special Registers Altered:
90 # Store Doubleword with Post-Update Indexed
105 Let the effective address (EA) be the sum (RA)+ (RB).
107 (RS) is stored into the doubleword in storage
110 EA is placed into register RA.
112 If RA=0, the instruction form is invalid.
114 Special Registers Altered: