1 <!-- This defines DRAFT instructions described in SV -->
3 <!-- This defines instructions that store from a register to RAM -->
4 <!-- Effective Address is always RA, and the usual EA is stored late in RA -->
6 # Store Byte with Post-Update Indexed
16 MEM(ea, 1) <- (RS)[XLEN-8:XLEN-1]
21 Let the effective address (EA) be the sum (RA)+ (RB).
23 (RS)[56:63] are stored into the byte in storage addressed by EA.
25 EA is placed into register RA.
27 If RA=0, the instruction form is invalid.
29 Special Registers Altered:
33 # Store Halfword with Post-Update Indexed
43 MEM(ea, 2) <- (RS)[XLEN-16:XLEN-1]
48 Let the effective address (EA) be the sum (RA)+ (RB).
50 (RS)[56:63] are stored into the byte in storage addressed by EA.
52 EA is placed into register RA.
54 If RA=0, the instruction form is invalid
56 Special Registers Altered:
60 # Store Word with Post-Update Indexed
70 MEM(ea, 4) <- (RS)[XLEN-32:XLEN-1]
75 Let the effective address (EA) be the sum (RA)+ (RB).
77 (RS)[32:63] are stored into the word in storage addressed by RA.
79 EA is placed into register RA.
81 If RA=0, the instruction form is invalid.
83 Special Registers Altered:
87 # Store Doubleword with Post-Update Indexed
102 Let the effective address (EA) be the sum (RA)+ (RB).
104 (RS) is stored into the doubleword in storage addressed by RA.
106 EA is placed into register RA.
108 If RA=0, the instruction form is invalid.
110 Special Registers Altered: