openpower/isa/pifixedstoreshift.mdwn

   1 <!-- This defines DRAFT instructions described in SV -->
   2
   3 <!-- This defines instructions that store from a register to RAM -->
   4 <!-- Effective Address is always RA, and the usual EA is stored late in RA -->
   5
   6 # Store Byte with Post-Update Indexed
   7
   8 X-Form
   9
  10 * stbupx RS,RA,RB
  11
  12 Pseudo-code:
  13
  14     EA <- (RA) + (RB)
  15     ea <- (RA)
  16     MEM(ea, 1) <- (RS)[XLEN-8:XLEN-1]
  17     RA <- EA
  18
  19 Description:
  20
  21     Let the effective address (EA) be the sum (RA)+ (RB).
  22
  23     (RS)[56:63] are stored into the byte in storage addressed by EA.
  24
  25     EA is placed into register RA.
  26
  27     If RA=0, the instruction form is invalid.
  28
  29 Special Registers Altered:
  30
  31     None
  32
  33 # Store Halfword with Post-Update Indexed
  34
  35 X-Form
  36
  37 * sthupx RS,RA,RB
  38
  39 Pseudo-code:
  40
  41     EA <- (RA) + (RB)
  42     ea <- (RA)
  43     MEM(ea, 2) <- (RS)[XLEN-16:XLEN-1]
  44     RA <- EA
  45
  46 Description:
  47
  48     Let the effective address (EA) be the sum (RA)+ (RB).
  49
  50     (RS)[56:63] are stored into the byte in storage addressed by EA.
  51
  52     EA is placed into register RA.
  53
  54     If RA=0, the instruction form is invalid
  55
  56 Special Registers Altered:
  57
  58     None
  59
  60 # Store Word with Post-Update Indexed
  61
  62 X-Form
  63
  64 * stwupx RS,RA,RB
  65
  66 Pseudo-code:
  67
  68     EA <- (RA) + (RB)
  69     ea <- (RA)
  70     MEM(ea, 4) <- (RS)[XLEN-32:XLEN-1]
  71     RA <- EA
  72
  73 Description:
  74
  75     Let the effective address (EA) be the sum (RA)+ (RB).
  76
  77     (RS)[32:63] are stored into the word in storage addressed by RA.
  78
  79     EA is placed into register RA.
  80
  81     If RA=0, the instruction form is invalid.
  82
  83 Special Registers Altered:
  84
  85     None
  86
  87 # Store Doubleword with Post-Update Indexed
  88
  89 X-Form
  90
  91 * stdupx RS,RA,RB
  92
  93 Pseudo-code:
  94
  95     EA <- (RA) + (RB)
  96     ea <- (RA)
  97     MEM(ea, 8) <- (RS)
  98     RA <- EA
  99
 100 Description:
 101
 102     Let the effective address (EA) be the sum (RA)+ (RB).
 103
 104     (RS) is stored into the doubleword in storage addressed by RA.
 105
 106     EA is placed into register RA.
 107
 108     If RA=0, the instruction form is invalid.
 109
 110 Special Registers Altered:
 111
 112     None
 113