openpower/isa/pifixedstoreshift.mdwn

   1 <!-- This defines DRAFT instructions described in SV -->
   2
   3 <!-- This defines instructions that store from a register to RAM -->
   4 <!-- Effective Address is always RA, and the usual EA is stored late in RA -->
   5
   6 <!-- https://bugs.libre-soc.org/show_bug.cgi?id=1055 -->
   7 <!-- https://libre-soc.org/openpower/sv/rfc/ls004/ -->
   8
   9 # Store Byte with Post-Update Indexed
  10
  11 Z23-Form
  12
  13 * stbupsx RS,RA,RB,SH
  14
  15 Pseudo-code:
  16
  17     EA <- (RA) + (RB)<<(SH+1)
  18     ea <- (RA)
  19     MEM(ea, 1) <- (RS)[XLEN-8:XLEN-1]
  20     RA <- EA
  21
  22 Description:
  23
  24     Let the effective address (EA) be the sum of the contents of
  25     register RB shifted by (SH+1), and the contents of register RA.
  26
  27     (RS)[56:63] are stored into the byte in storage addressed by EA.
  28
  29     EA is placed into register RA.
  30
  31     If RA=0, the instruction form is invalid.
  32
  33 Special Registers Altered:
  34
  35     None
  36
  37 # Store Halfword with Post-Update Indexed
  38
  39 Z23-Form
  40
  41 * sthupsx RS,RA,RB,SH
  42
  43 Pseudo-code:
  44
  45     EA <- (RA) + (RB)<<(SH+1)
  46     ea <- (RA)
  47     MEM(ea, 2) <- (RS)[XLEN-16:XLEN-1]
  48     RA <- EA
  49
  50 Description:
  51
  52     Let the effective address (EA) be the sum of the contents of
  53     register RB shifted by (SH+1), and the contents of register RA.
  54
  55     (RS)[56:63] are stored into the byte in storage addressed by EA.
  56
  57     EA is placed into register RA.
  58
  59     If RA=0, the instruction form is invalid
  60
  61 Special Registers Altered:
  62
  63     None
  64
  65 # Store Word with Post-Update Indexed
  66
  67 Z23-Form
  68
  69 * stwupsx RS,RA,RB
  70
  71 Pseudo-code:
  72
  73     EA <- (RA) + (RB)
  74     ea <- (RA)
  75     MEM(ea, 4) <- (RS)[XLEN-32:XLEN-1]
  76     RA <- EA
  77
  78 Description:
  79
  80     Let the effective address (EA) be the sum (RA)+ (RB).
  81
  82     (RS)[32:63] are stored into the word in storage addressed by RA.
  83
  84     EA is placed into register RA.
  85
  86     If RA=0, the instruction form is invalid.
  87
  88 Special Registers Altered:
  89
  90     None
  91
  92 # Store Doubleword with Post-Update Indexed
  93
  94 Z23-Form
  95
  96 * stdupsx RS,RA,RB
  97
  98 Pseudo-code:
  99
 100     EA <- (RA) + (RB)
 101     ea <- (RA)
 102     MEM(ea, 8) <- (RS)
 103     RA <- EA
 104
 105 Description:
 106
 107     Let the effective address (EA) be the sum (RA)+ (RB).
 108
 109     (RS) is stored into the doubleword in storage addressed by RA.
 110
 111     EA is placed into register RA.
 112
 113     If RA=0, the instruction form is invalid.
 114
 115 Special Registers Altered:
 116
 117     None
 118