openpower/isa/pifixedstoreshift.mdwn

   1 <!-- This defines DRAFT instructions described in SV -->
   2
   3 <!-- This defines instructions that store from a register to RAM -->
   4 <!-- Effective Address is always RA, and the usual EA is stored late in RA -->
   5
   6 <!-- https://bugs.libre-soc.org/show_bug.cgi?id=1055 -->
   7 <!-- https://libre-soc.org/openpower/sv/rfc/ls004/ -->
   8
   9 # Store Byte with Post-Update Indexed
  10
  11 Z23-Form
  12
  13 * stbupsx RS,RA,RB
  14
  15 Pseudo-code:
  16
  17     EA <- (RA) + (RB)
  18     ea <- (RA)
  19     MEM(ea, 1) <- (RS)[XLEN-8:XLEN-1]
  20     RA <- EA
  21
  22 Description:
  23
  24     Let the effective address (EA) be the sum (RA)+ (RB).
  25
  26     (RS)[56:63] are stored into the byte in storage addressed by EA.
  27
  28     EA is placed into register RA.
  29
  30     If RA=0, the instruction form is invalid.
  31
  32 Special Registers Altered:
  33
  34     None
  35
  36 # Store Halfword with Post-Update Indexed
  37
  38 Z23-Form
  39
  40 * sthupsx RS,RA,RB
  41
  42 Pseudo-code:
  43
  44     EA <- (RA) + (RB)
  45     ea <- (RA)
  46     MEM(ea, 2) <- (RS)[XLEN-16:XLEN-1]
  47     RA <- EA
  48
  49 Description:
  50
  51     Let the effective address (EA) be the sum (RA)+ (RB).
  52
  53     (RS)[56:63] are stored into the byte in storage addressed by EA.
  54
  55     EA is placed into register RA.
  56
  57     If RA=0, the instruction form is invalid
  58
  59 Special Registers Altered:
  60
  61     None
  62
  63 # Store Word with Post-Update Indexed
  64
  65 Z23-Form
  66
  67 * stwupsx RS,RA,RB
  68
  69 Pseudo-code:
  70
  71     EA <- (RA) + (RB)
  72     ea <- (RA)
  73     MEM(ea, 4) <- (RS)[XLEN-32:XLEN-1]
  74     RA <- EA
  75
  76 Description:
  77
  78     Let the effective address (EA) be the sum (RA)+ (RB).
  79
  80     (RS)[32:63] are stored into the word in storage addressed by RA.
  81
  82     EA is placed into register RA.
  83
  84     If RA=0, the instruction form is invalid.
  85
  86 Special Registers Altered:
  87
  88     None
  89
  90 # Store Doubleword with Post-Update Indexed
  91
  92 Z23-Form
  93
  94 * stdupsx RS,RA,RB
  95
  96 Pseudo-code:
  97
  98     EA <- (RA) + (RB)
  99     ea <- (RA)
 100     MEM(ea, 8) <- (RS)
 101     RA <- EA
 102
 103 Description:
 104
 105     Let the effective address (EA) be the sum (RA)+ (RB).
 106
 107     (RS) is stored into the doubleword in storage addressed by RA.
 108
 109     EA is placed into register RA.
 110
 111     If RA=0, the instruction form is invalid.
 112
 113 Special Registers Altered:
 114
 115     None
 116