openpower/isa/pifploadshift.mdwn

   1 <!-- X Instructions here described in PowerISA Version 3.0 B Book 1 -->
   2
   3 <!-- Section 4.6.1 Floating-point storage access instructions. P 140 - 143 -->
   4
   5 # Load Floating-Point Single with Post-Update Shifted Indexed
   6
   7 X-Form
   8
   9 * lfsupsx FRT,RA,RB,SH
  10
  11 Pseudo-code:
  12
  13     EA <- (RA) + (RB)<<(SH+1)
  14     FRT <- DOUBLE(MEM(RA, 4))
  15     RA <- EA
  16
  17 Description:
  18
  19     Let the effective address (EA) be the sum of the contents of
  20     register RB shifted by (SH+1), and the contents of register RA.
  21
  22     The word in storage addressed by EA is interpreted as
  23     a floating-point single-precision operand. This word is
  24     converted to floating-point double format (see
  25     page 138) and placed into register FRT.
  26
  27     EA is placed into register RA.
  28
  29     If RA=0, the instruction form is invalid.
  30
  31 Special Registers Altered:
  32
  33     None
  34
  35 # Load Floating-Point Double with Post-Update Indexed
  36
  37 X-Form
  38
  39 * lfdupsx FRT,RA,RB
  40
  41 Pseudo-code:
  42
  43     EA <- (RA) + (RB)
  44     FRT <- MEM(RA, 8)
  45     RA <- EA
  46
  47 Description:
  48
  49     Let the effective address (EA) be the sum (RA)+(RB).
  50
  51     The doubleword in storage addressed by EA is loaded
  52     into register FRT.
  53
  54     EA is placed into register RA.
  55
  56     If RA=0, the instruction form is invalid.
  57
  58 Special Registers Altered:
  59
  60     None
  61