openpower/isa/pifpstoreshift.mdwn

   1 <!-- X Instructions here described in PowerISA Version 3.0 B Book 1 -->
   2
   3 <!-- Section 4.6.3 Floating-point store instructions. P 144 - 147 -->
   4
   5 # Store Floating-Point Single with Update Shifted Indexed
   6
   7 X-Form
   8
   9 * stfsupsx FRS,RA,RB,SH
  10
  11 Pseudo-code:
  12
  13     EA <- (RA) + (RB)<<(SH+1)
  14     MEM(RA, 4)<- SINGLE( (FRS) )
  15     RA <- EA
  16
  17 Description:
  18
  19     Let the effective address (EA) be the sum of the contents of
  20     register RB shifted by (SH+1), and the contents of register RA.
  21
  22     The contents of register FRS are converted to single
  23     format (see page 142) and stored into the word in stor-
  24     age addressed by RA.
  25
  26     EA is placed into register RA.
  27
  28     If RA=0, the instruction form is invalid.
  29
  30 Special Registers Altered:
  31
  32     None
  33
  34 # Store Floating-Point Double with Update Indexed
  35
  36 X-Form
  37
  38 * stfdupsx FRS,RA,RB
  39
  40 Pseudo-code:
  41
  42     EA <- (RA) + (RB)
  43     MEM(RA, 8)<- (FRS)
  44     RA <- EA
  45
  46 Description:
  47
  48     Let the effective address (EA) be the sum (RA)+(RB).
  49
  50     The contents of register FRS are stored into the dou-
  51     bleword in storage addressed by RA.
  52
  53     EA is placed into register RA.
  54
  55     If RA=0, the instruction form is invalid.
  56
  57 Special Registers Altered:
  58
  59     None
  60