1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
3 <!-- Section 4.4.4 Move To/From System Register Instructions pages 970 - 1038 -->
5 <!-- Section 4.4.4 Move To/From System Register Instructions pages 970 - 1038 -->
6 <!-- Section 3.3.17 Move To/From System Register Instructions Page 120 -->
7 <!-- Section 4.3.2 Data Cache Instructions Page 850 -->
9 <!-- This needs checking again -->
11 <!-- The Move To Special Purpose Register and Move From Special Purpose Register -->
12 <!-- instructions are described in Book I, but only at the level available to an -->
13 <!-- application programmer. For example, no mention is made there of registers that -->
14 <!-- can be accessed only in privileged state. The descriptions of these instructions -->
15 <!-- given below extend the descriptions given in Book I, but do not list Special -->
16 <!-- Purpose Registers that are implementation-dependent. In the descriptions of -->
17 <!-- these instructions given in below, the “defined” SPR numbers are the SPR -->
18 <!-- numbers shown in the Figure 18 for the instruction and the -->
19 <!-- implementation-specific SPR numbers that are implemented, and similarly for -->
20 <!-- “defined” registers. All other SPR numbers are undefined for the instruction. -->
21 <!-- (Implementation-specific SPR numbers that are not implemented are considered to -->
22 <!-- be undefined.) When an SPR is defined for mtspr and undefined for mfspr, or -->
23 <!-- vice versa, a hyphen appears in the column for the instruction for which the -->
24 <!-- SPR number is undefined. -->
30 # Move To Special Purpose Register
40 case(13): see(Book_III_p974)
41 case(808, 809, 810, 811):
43 if length(SPR(n)) = 64 then
46 SPR(n) <- (RS) [32:63]
48 Special Registers Altered:
54 # Move From Special Purpose Register
64 case(129): see(Book_III_p975)
65 case(808, 809, 810, 811):
67 if length(SPR(n)) = 64 then
70 RT <- [0]*32 || SPR(n)
72 Special Registers Altered:
76 <!-- Section 3.3.17 Move To/From System Register Instructions Page 120 -->
78 # Move to CR from XER Extended
86 CR[4*BF+32:4*BF+35] <- XER[OV] || XER[OV32] || XER[CA] || XER[CA32]
88 Special Registers Altered:
92 # Move To One Condition Register Field
104 CR[4*n+32:4*n+35] <- (RS)[4*n+32:4*n+35]
106 Special Registers Altered:
108 CR field selected by FXM
110 # Move To Condition Register Fields
120 CR[4*n+32:4*n+35] <- (RS)[4*n+32:4*n+35]
122 Special Registers Altered:
124 CR fields selected by mask
126 # Move From One Condition Register Field
137 if (done = 0) & (FXM[n] = 1) then
138 RT[4*n+32:4*n+35] <- CR[4*n+32:4*n+35]
141 Special Registers Altered:
145 # Move From Condition Register
155 Special Registers Altered:
167 if CR[4*BFA+32] = 1 then
168 RT <- 0xFFFF_FFFF_FFFF_FFFF
169 else if CR[4*BFA+33]=1 then
170 RT <- 0x0000_0000_0000_0001
172 RT <- 0x0000_0000_0000_0000
174 Special Registers Altered:
178 # Set Boolean Condition
186 RT <- (CR[BI + 32] = 1) ? 1 : 0
188 Special Registers Altered:
192 # Set Boolean Condition Reverse
200 RT <- (CR[BI + 32] = 1) ? 0 : 1
202 Special Registers Altered:
206 # Set Negative Boolean Condition
214 RT <- (CR[BI + 32] = 1) ? -1 : 0
216 Special Registers Altered:
220 # Set Negative Boolean Condition Reverse
228 RT <- (CR[BI + 32] = 1) ? 0 : -1
230 Special Registers Altered:
234 <!-- Out of order from the PDF. Page 977 -->
236 # Move To Machine State Register
245 MSR[48] <- (RS)[48] | (RS)[49]
246 MSR[58] <- (RS)[58] | (RS)[49]
247 MSR[59] <- (RS)[59] | (RS)[49]
248 MSR[32:40] <- (RS)[32:40]
249 MSR[42:47] <- (RS)[42:47]
250 MSR[49:50] <- (RS)[49:50]
251 MSR[52:57] <- (RS)[52:57]
252 MSR[60:62] <- (RS)[60:62]
257 Special Registers Altered:
261 # Move To Machine State Register
270 if (MSR[29:31] != 0b010) | ((RS)[29:31] != 0b000) then
271 MSR[29:31] <- (RS)[29:31]
272 MSR[48] <- (RS)[48] | (RS)[49]
273 MSR[58] <- (RS)[58] | (RS)[49]
274 MSR[59] <- (RS)[59] | (RS)[49]
275 MSR[0:2] <- (RS)[0:2]
276 MSR[4:28] <- (RS)[4:28]
277 MSR[32:40] <- (RS)[32:40]
278 MSR[42:47] <- (RS)[42:47]
279 MSR[49:50] <- (RS)[49:50]
280 MSR[52:57] <- (RS)[52:57]
281 MSR[60:62] <- (RS)[60:62]
286 Special Registers Altered:
290 # Move From Machine State Register
300 Special Registers Altered:
304 <!-- Section 4.3.2 Data Cache Instructions Page 850 -->
306 # Data Cache Block set to Zero
314 if RA = 0 then b <- 0
318 Special Registers Altered:
322 <!-- Section 5.9.3.3 TLB Management Instructions Page 1033 -->
324 # TLB Invalidate Entry
328 * tlbie RB,RS,RIC,PRS,R
334 Special Registers Altered:
338 <!-- MISSING tlbiel page 1038 -->
339 <!-- MISSING tlbsync page 1042 -->