openpower/isa/sprset.mdwn

   1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
   2
   3 <!-- Section 4.4.4 Move To/From System Register Instructions pages 970 - 1038 -->
   4
   5 <!-- Section 4.4.4 Move To/From System Register Instructions pages 970 - 1038 -->
   6 <!-- Section 3.3.17 Move To/From System Register Instructions Page 120 -->
   7 <!-- Section 4.3.2 Data Cache Instructions Page 850 -->
   8
   9 <!-- This needs checking again -->
  10
  11 <!-- The Move To Special Purpose Register and Move From Special Purpose Register -->
  12 <!-- instructions are described in Book I, but only at the level available to an -->
  13 <!-- application programmer. For example, no mention is made there of registers that -->
  14 <!-- can be accessed only in privileged state. The descriptions of these instructions -->
  15 <!-- given below extend the descriptions given in Book I, but do not list Special -->
  16 <!-- Purpose Registers that are implementation-dependent. In the descriptions of -->
  17 <!-- these instructions given in below, the “defined” SPR numbers are the SPR -->
  18 <!-- numbers shown in the Figure 18 for the instruction and the -->
  19 <!-- implementation-specific SPR numbers that are implemented, and similarly for -->
  20 <!-- “defined” registers. All other SPR numbers are undefined for the instruction. -->
  21 <!-- (Implementation-specific SPR numbers that are not implemented are considered to -->
  22 <!-- be undefined.) When an SPR is defined for mtspr and undefined for mfspr, or -->
  23 <!-- vice versa, a hyphen appears in the column for the instruction for which the -->
  24 <!-- SPR number is undefined. -->
  25
  26
  27
  28 <!-- Page 974 -->
  29
  30 # Move To Special Purpose Register
  31
  32 XFX-Form
  33
  34 * mtspr spr,RS
  35
  36 Pseudo-code:
  37
  38     n <- spr
  39     switch (n)
  40       case(13): see(Book_III_p974)
  41       case(808, 809, 810, 811):
  42       default:
  43         if length(SPR(n)) = 64 then
  44           SPR(n) <- (RS)
  45         else
  46           SPR(n) <- (RS) [32:63]
  47
  48 Special Registers Altered:
  49
  50     See spec 3.3.17
  51
  52 <!-- Page 975 -->
  53
  54 # Move From Special Purpose Register
  55
  56 XFX-Form
  57
  58 * mfspr RT,spr
  59
  60 Pseudo-code:
  61
  62     n <- spr
  63     switch (n)
  64       case(129): see(Book_III_p975)
  65       case(808, 809, 810, 811):
  66       default:
  67         if length(SPR(n)) = 64 then
  68           RT <- SPR(n)
  69         else
  70           RT <- [0]*32 || SPR(n)
  71
  72 Special Registers Altered:
  73
  74     None
  75
  76 <!-- Section 3.3.17 Move To/From System Register Instructions Page 120 -->
  77
  78 # Move to CR from XER Extended
  79
  80 X-Form
  81
  82 * mcrxrx BF
  83
  84 Pseudo-code:
  85
  86     CR[4*BF+32:4*BF+35] <-  XER[OV] || XER[OV32] || XER[CA] || XER[CA32]
  87
  88 Special Registers Altered:
  89
  90     CR field BF
  91
  92 # Move To One Condition Register Field
  93
  94 XFX-Form
  95
  96 * mtocrf FXM,RS
  97
  98 Pseudo-code:
  99
 100     n <- 7
 101     do i = 7 to 0
 102       if FXM[i] = 1 then
 103         n <- i
 104     CR[4*n+32:4*n+35] <- (RS)[4*n+32:4*n+35]
 105
 106 Special Registers Altered:
 107
 108     CR field selected by FXM
 109
 110 # Move To Condition Register Fields
 111
 112 XFX-Form
 113
 114 * mtcrf FXM,RS
 115
 116 Pseudo-code:
 117
 118     do n = 0 to 7
 119       if FXM[n] = 1 then
 120         CR[4*n+32:4*n+35] <- (RS)[4*n+32:4*n+35]
 121
 122 Special Registers Altered:
 123
 124     CR fields selected by mask
 125
 126 # Move From One Condition Register Field
 127
 128 XFX-Form
 129
 130 * mfocrf RT,FXM
 131
 132 Pseudo-code:
 133
 134     done <- 0
 135     RT <- [0]*64
 136     do n = 0 to 7
 137       if (done = 0) & (FXM[n] = 1) then
 138         RT[4*n+32:4*n+35] <- CR[4*n+32:4*n+35]
 139         done <- 1
 140
 141 Special Registers Altered:
 142
 143     None
 144
 145 # Move From Condition Register
 146
 147 XFX-Form
 148
 149 * mfcr RT
 150
 151 Pseudo-code:
 152
 153     RT <- [0]*32 || CR
 154
 155 Special Registers Altered:
 156
 157     None
 158
 159 # Set Boolean
 160
 161 X-Form
 162
 163 * setb RT,BFA
 164
 165 Pseudo-code:
 166
 167     if CR[4*BFA+32] = 1 then
 168        RT <- 0xFFFF_FFFF_FFFF_FFFF
 169     else if CR[4*BFA+33]=1 then
 170        RT <- 0x0000_0000_0000_0001
 171     else
 172        RT <- 0x0000_0000_0000_0000
 173
 174 Special Registers Altered:
 175
 176     None
 177
 178 # Set Boolean Condition
 179
 180 X-Form
 181
 182 * setbc RT,BI
 183
 184 Pseudo-code:
 185
 186     RT <- (CR[BI + 32] = 1) ? 1 : 0
 187
 188 Special Registers Altered:
 189
 190     None
 191
 192 # Set Boolean Condition Reverse
 193
 194 X-Form
 195
 196 * setbcr RT,BI
 197
 198 Pseudo-code:
 199
 200     RT <- (CR[BI + 32] = 1) ? 0 : 1
 201
 202 Special Registers Altered:
 203
 204     None
 205
 206 # Set Negative Boolean Condition
 207
 208 X-Form
 209
 210 * setnbc RT,BI
 211
 212 Pseudo-code:
 213
 214     RT <- (CR[BI + 32] = 1) ? -1 : 0
 215
 216 Special Registers Altered:
 217
 218     None
 219
 220 # Set Negative Boolean Condition Reverse
 221
 222 X-Form
 223
 224 * setnbcr RT,BI
 225
 226 Pseudo-code:
 227
 228     RT <- (CR[BI + 32] = 1) ? 0 : -1
 229
 230 Special Registers Altered:
 231
 232     None
 233
 234 <!-- Out of order from the PDF. Page 977 -->
 235
 236 # Move To Machine State Register
 237
 238 X-Form
 239
 240 * mtmsr RS,L1
 241
 242 Pseudo-code:
 243
 244     if L1 = 0 then
 245         MSR[48] <- (RS)[48] | (RS)[49]
 246         MSR[58] <- (RS)[58] | (RS)[49]
 247         MSR[59] <- (RS)[59] | (RS)[49]
 248         MSR[32:40] <- (RS)[32:40]
 249         MSR[42:47] <- (RS)[42:47]
 250         MSR[49:50] <- (RS)[49:50]
 251         MSR[52:57] <- (RS)[52:57]
 252         MSR[60:62] <- (RS)[60:62]
 253     else
 254         MSR[48] <- (RS)[48]
 255         MSR[62] <- (RS)[62]
 256
 257 Special Registers Altered:
 258
 259     MSR
 260
 261 # Move To Machine State Register
 262
 263 X-Form
 264
 265 * mtmsrd RS,L1
 266
 267 Pseudo-code:
 268
 269     if L1 = 0 then
 270         if (MSR[29:31] != 0b010) | ((RS)[29:31] != 0b000) then
 271             MSR[29:31] <- (RS)[29:31]
 272         MSR[48] <- (RS)[48] | (RS)[49]
 273         MSR[58] <- (RS)[58] | (RS)[49]
 274         MSR[59] <- (RS)[59] | (RS)[49]
 275         MSR[0:2] <- (RS)[0:2]
 276         MSR[4:28] <- (RS)[4:28]
 277         MSR[32:40] <- (RS)[32:40]
 278         MSR[42:47] <- (RS)[42:47]
 279         MSR[49:50] <- (RS)[49:50]
 280         MSR[52:57] <- (RS)[52:57]
 281         MSR[60:62] <- (RS)[60:62]
 282     else
 283         MSR[48] <- (RS)[48]
 284         MSR[62] <- (RS)[62]
 285
 286 Special Registers Altered:
 287
 288     MSR
 289
 290 # Move From Machine State Register
 291
 292 X-Form
 293
 294 * mfmsr RT
 295
 296 Pseudo-code:
 297
 298     RT <- MSR
 299
 300 Special Registers Altered:
 301
 302     None
 303
 304 <!-- Section 4.3.2 Data Cache Instructions Page 850 -->
 305
 306 # Data Cache Block set to Zero
 307
 308 X-Form
 309
 310 * dcbz RA,RB
 311
 312 Pseudo-code:
 313
 314     if RA = 0 then b <- 0
 315     else           b <-(RA)
 316     EA <- b + (RB)
 317
 318 Special Registers Altered:
 319
 320     None
 321
 322 <!-- Section 5.9.3.3 TLB Management Instructions Page 1033 -->
 323
 324 # TLB Invalidate Entry
 325
 326 X-Form
 327
 328 * tlbie RB,RS,RIC,PRS,R
 329
 330 Pseudo-code:
 331
 332     IS <- (RB) [52:53]
 333
 334 Special Registers Altered:
 335
 336     None
 337
 338 <!-- MISSING tlbiel page 1038 -->
 339 <!-- MISSING tlbsync page 1042 -->