1 <!-- Instructions here part of Draft SVP64 Vectorised Branch -->
3 <!-- Section 2.4 Branch Instructions. Pages 33 - 39 -->
5 <!-- The sequence of instruction execution can be changed by the Branch -->
6 <!-- instructions. Because all instructions are on word boundaries, bits 62 and 63 -->
7 <!-- of the generated branch target address are ignored by the processor in -->
8 <!-- performing the branch. -->
10 <!-- target_addr specifies the branch target address. -->
12 <!-- If AA=0 then the branch target address is the sum of LI || 0b00 sign-extended -->
13 <!-- and the address of this instruction, with the high-order 32 bits of the branch -->
14 <!-- target address set to 0 in 32-bit mode. -->
16 <!-- If AA=1 then the branch target address is the value LI || 0b00 sign-extended, -->
17 <!-- with the high-order 32 bits of the branch target address set to 0 in 32-bit -->
20 <!-- If LK=1 then the effective address of the instruction following the Branch -->
21 <!-- instruction is placed into the Link Register. -->
27 * sv.bc BO,BI,target_addr (AA=0 LK=0)
28 * sv.bca BO,BI,target_addr (AA=1 LK=0)
29 * sv.bcl BO,BI,target_addr (AA=0 LK=1)
30 * sv.bcla BO,BI,target_addr (AA=1 LK=1)
34 # get SVP64 extended CR field 0..127
35 # SVCRf = sVP64EXTRA(BI>>2)
37 # new_srcstep, CRbits = SVSTATE_NEXT(srcstep)
40 # select predicate bit or zero/one
41 # XXX if predicate[srcstep] then
42 # XXX if BRc = 1 then # CR0 vectorised
43 # XXX CR{SVCRf+srcstep} = CRbits
44 # XXX testbit = CRbits[BI & 0b11]
50 if (mode_is_64bit) then M <- 0
52 if ¬BO[2] then CTR <- CTR - 1
53 ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3])
54 # actual element test here
55 cond_ok <- BO[0] | ¬(testbit ^ BO[1])
56 # test for VL to be set (and exit)
57 if VLSET & ((cond_ok & ctr_ok) = VSb) then
59 SVSTATE[7:13] <- (srcstep+1)
61 SVSTATE[7:13] <- srcstep
63 # XXX if svstep_mode then
64 # XXX SVSTATE.srcstep = new_srcstep
68 # in ALL mode only try branching at end of loop
71 # test early-exit. ALL will exit if cond_ok fails
72 if ¬(cond_ok & ctr_ok) then
76 if test_branch & ctr_ok & cond_ok then
77 if AA then NIA <-iea EXTS(BD || 0b00)
78 else NIA <-iea CIA + EXTS(BD || 0b00)
81 if LK & lr_ok then LR <-iea CIA + 4
83 Special Registers Altered:
88 # Branch Conditional to Link Register
92 * sv.bclr BO,BI,BH (LK=0)
93 * sv.bclrl BO,BI,BH (LK=1)
97 if (mode_is_64bit) then M <- 0
99 if ¬BO[2] then CTR <- CTR - 1
100 ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3])
101 cond_ok <- BO[0] | ¬(CR[BI+32] ^ BO[1])
103 if ctr_ok & cond_ok then
104 NIA <-iea LR[0:61] || 0b00
106 if LK & lr_ok then LR <-iea CIA + 4
108 Special Registers Altered: