openpower/isa/svbranch.mdwn

   1 <!-- Instructions here part of Draft SVP64 Vectorised Branch -->
   2
   3 <!-- Section 2.4 Branch Instructions. Pages 33 - 39 -->
   4
   5 <!-- The sequence of instruction execution can be changed by the Branch -->
   6 <!-- instructions. Because all instructions are on word boundaries, bits 62 and 63 -->
   7 <!-- of the generated branch target address are ignored by the processor in -->
   8 <!-- performing the branch. -->
   9
  10 <!-- target_addr specifies the branch target address. -->
  11
  12 <!-- If AA=0 then the branch target address is the sum of LI || 0b00 sign-extended -->
  13 <!-- and the address of this instruction, with the high-order 32 bits of the branch -->
  14 <!-- target address set to 0 in 32-bit mode. -->
  15
  16 <!-- If AA=1 then the branch target address is the value LI || 0b00 sign-extended, -->
  17 <!-- with the high-order 32 bits of the branch target address set to 0 in 32-bit -->
  18 <!-- mode. -->
  19
  20 <!-- If LK=1 then the effective address of the instruction following the Branch -->
  21 <!-- instruction is placed into the Link Register. -->
  22
  23 # Branch Conditional
  24
  25 B-Form
  26
  27 * sv.bc BO,BI,target_addr (AA=0 LK=0)
  28 * sv.bca BO,BI,target_addr (AA=1 LK=0)
  29 * sv.bcl BO,BI,target_addr (AA=0 LK=1)
  30 * sv.bcla BO,BI,target_addr (AA=1 LK=1)
  31
  32 Pseudo-code:
  33
  34     # get SVP64 extended CR field 0..127
  35     # SVCRf = sVP64EXTRA(BI>>2)
  36     # if svstep_mode then
  37     #    new_srcstep, CRbits = SVSTATE_NEXT(srcstep)
  38     # else
  39     #    CRbits = CR{SVCRf}
  40     # select predicate bit or zero/one
  41     # XXX if predicate[srcstep] then
  42     # XXX     if BRc = 1 then # CR0 vectorised
  43     # XXX         CR{SVCRf+srcstep} = CRbits
  44     # XXX         testbit = CRbits[BI & 0b11]
  45     if sz then
  46         testbit = SNZ
  47     else
  48         testbit <- CR[BI+32]
  49     # test CTR mode here
  50     if (mode_is_64bit) then M <- 0
  51     else M <- 32
  52     if ¬BO[2] then CTR <- CTR - 1
  53     ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3])
  54     # actual element test here
  55     cond_ok <- BO[0] | ¬(testbit ^ BO[1])
  56     # test for VL to be set (and exit)
  57     if VLSET & ((cond_ok & ctr_ok) = VSb) then
  58         if VLI then
  59             SVSTATE[7:13] <- (srcstep+1)
  60         else
  61             SVSTATE[7:13] <- srcstep
  62         end_loop <- 0b1
  63     # XXX if svstep_mode then
  64     # XXX   SVSTATE.srcstep = new_srcstep
  65     # actual branch
  66     test_branch <- 0b1
  67     if ALL then
  68         # in ALL mode only try branching at end of loop
  69         if ¬end_loop then
  70             test_branch <- 0b0
  71         # test early-exit. ALL will exit if cond_ok fails
  72         if ¬(cond_ok & ctr_ok) then
  73             end_loop <- 0b1
  74             test_branch <- 0b0
  75     lr_ok <- LRu
  76     if test_branch & ctr_ok & cond_ok then
  77       if AA then NIA <-iea EXTS(BD || 0b00)
  78       else       NIA <-iea CIA + EXTS(BD || 0b00)
  79       lr_ok <- 0b1
  80       end_loop <- 0b1
  81     if LK & lr_ok then LR <-iea CIA + 4
  82
  83 Special Registers Altered:
  84
  85     CTR                    (if BO2=0)
  86     LR                       (if LK=1)
  87
  88 # Branch Conditional to Link Register
  89
  90 XL-Form
  91
  92 * sv.bclr BO,BI,BH (LK=0)
  93 * sv.bclrl BO,BI,BH (LK=1)
  94
  95 Pseudo-code:
  96
  97     if (mode_is_64bit) then M <- 0
  98     else M <- 32
  99     if ¬BO[2]  then CTR <- CTR - 1
 100     ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3])
 101     cond_ok <- BO[0] | ¬(CR[BI+32] ^  BO[1])
 102     lr_ok <- LRu
 103     if ctr_ok & cond_ok then
 104         NIA <-iea LR[0:61] || 0b00
 105         lr_ok <- 0b1
 106     if LK & lr_ok then LR <-iea CIA + 4
 107
 108 Special Registers Altered:
 109
 110     CTR                    (if BO2=0)
 111     LR                       (if LK=1)
 112