openpower/isa/svfixedarith.mdwn

   1 # [DRAFT] Multiply and Add Extended Doubleword Unsigned
   2
   3 VA-Form
   4
   5 * maddedu RT,RA,RB,RC
   6
   7 Pseudo-code:
   8
   9     <!-- SVP64: RA,RB,RC,RT have EXTRA2, RS as below
  10     <!-- bit 8 of EXTRA is set  : RS.[s|v]=RT.[s|v]+MAXVL
  11     <!-- bit 8 of EXTRA is clear: RS.[s|v]=RC.[s|v]
  12     prod[0:2*XLEN-1] <- (RA) * (RB)
  13     sum[0:2*XLEN-1] <- ([0] * XLEN || (RC)) + prod
  14     RT <- sum[XLEN:2*XLEN-1]
  15     RS <- sum[0:XLEN-1]
  16
  17 Special Registers Altered:
  18
  19     None
  20
  21 # [DRAFT] Multiply and Add Extended Doubleword Unsigned Signed
  22
  23 VA-Form
  24
  25 * maddedus RT,RA,RB,RC
  26
  27 Pseudo-code:
  28
  29     <!-- SVP64: RA,RB,RC,RT have EXTRA2, RS as below
  30     <!-- bit 8 of EXTRA is set  : RS.[s|v]=RT.[s|v]+MAXVL
  31     <!-- bit 8 of EXTRA is clear: RS.[s|v]=RC.[s|v]
  32     <!-- no MULUS, so do it manually -->
  33     prod[0:XLEN*2-1] <- [0] * (XLEN * 2)
  34     if (RB)[0] != 0 then
  35         prod[0:XLEN*2-1] <- -((RA) * -(RB))
  36     else
  37         prod[0:XLEN*2-1] <- (RA) * (RB)
  38     <!-- no EXTS2XL, so do it manually -->
  39     sum[0:XLEN*2-1] <- prod + (EXTSXL((RC)[0], 1) || (RC))
  40     RT <- sum[XLEN:2*XLEN-1]
  41     RS <- sum[0:XLEN-1]
  42
  43 Special Registers Altered:
  44
  45     None
  46
  47 # [DRAFT] Divide/Modulo Double-width Doubleword Unsigned
  48
  49 VA-Form
  50
  51 * divmod2du   RT,RA,RB,RC
  52
  53 Pseudo-code:
  54
  55     <!-- SVP64: RA,RB,RC,RT have EXTRA2, RS as below
  56     <!-- bit 8 of EXTRA is set  : RS.[s|v]=RT.[s|v]+MAXVL
  57     <!-- bit 8 of EXTRA is clear: RS.[s|v]=RC.[s|v]
  58     if ((RC) <u (RB)) & ((RB) != [0]*XLEN) then
  59         dividend[0:(XLEN*2)-1] <- (RC) || (RA)
  60         divisor[0:(XLEN*2)-1] <- [0]*XLEN || (RB)
  61         result <- dividend / divisor
  62         modulo <- dividend % divisor
  63         RT <- result[XLEN:(XLEN*2)-1]
  64         RS <- modulo[XLEN:(XLEN*2)-1]
  65         overflow <- 0
  66     else
  67         overflow <- 1
  68         RT <- [1]*XLEN
  69         RS <- [0]*XLEN
  70
  71 Special Registers Altered:
  72
  73     XER.OV
  74
  75 # [DRAFT] Double-width Shift Left Doubleword
  76
  77 VA2-Form
  78
  79 * dsld    RT,RA,RB,RC  (Rc=0)
  80 * dsld.   RT,RA,RB,RC  (Rc=1)
  81
  82 Pseudo-code:
  83
  84     n <- (RB)[58:63]
  85     v <- ROTL64((RA), n)
  86     mask <- MASK(0, 63-n)
  87     RT <- (v[0:63] & mask) | ((RC) & ¬mask)
  88     RS <- v[0:63] & ¬mask
  89     overflow <- 0             # relevant only when Rc=1
  90     if RS != [0]*64 then
  91         overflow <- 1         # relevant only when Rc=1
  92
  93 Special Registers Altered:
  94
  95     CR0                    (if Rc=1)
  96
  97 # [DRAFT] Double-width Shift Right Doubleword
  98
  99 VA2-Form
 100
 101 * dsrd    RT,RA,RB,RC  (Rc=0)
 102 * dsrd.   RT,RA,RB,RC  (Rc=1)
 103
 104 Pseudo-code:
 105
 106     n <- (RB)[58:63]
 107     v <- ROTL64((RA), 64-n)
 108     mask <- MASK(n, 63)
 109     RT <- (v[0:63] & mask) | ((RC) & ¬mask)
 110     RS <- v[0:63] & ¬mask
 111     overflow <- 0             # relevant only when Rc=1
 112     if RS != [0]*64 then
 113         overflow <- 1         # relevant only when Rc=1
 114
 115 Special Registers Altered:
 116
 117     CR0                    (if Rc=1)