1 # [DRAFT] Multiply and Add Extended Doubleword Unsigned
9 <!-- SVP64: RA,RB,RC,RT have EXTRA2, RS as below
10 <!-- bit 8 of EXTRA is set : RS.[s|v]=RT.[s|v]+MAXVL
11 <!-- bit 8 of EXTRA is clear: RS.[s|v]=RC.[s|v]
12 prod[0:2*XLEN-1] <- (RA) * (RB)
13 sum[0:2*XLEN-1] <- ([0] * XLEN || (RC)) + prod
14 RT <- sum[XLEN:2*XLEN-1]
17 Special Registers Altered:
21 # [DRAFT] Multiply and Add Extended Doubleword Unsigned Signed
25 * maddedus RT,RA,RB,RC
29 <!-- SVP64: RA,RB,RC,RT have EXTRA2, RS as below
30 <!-- bit 8 of EXTRA is set : RS.[s|v]=RT.[s|v]+MAXVL
31 <!-- bit 8 of EXTRA is clear: RS.[s|v]=RC.[s|v]
32 <!-- no MULUS, so do it manually -->
33 prod[0:XLEN*2-1] <- [0] * (XLEN * 2)
35 prod[0:XLEN*2-1] <- -((RA) * -(RB))
37 prod[0:XLEN*2-1] <- (RA) * (RB)
38 <!-- no EXTS2XL, so do it manually -->
39 sum[0:XLEN*2-1] <- prod + (EXTSXL((RC)[0], 1) || (RC))
40 RT <- sum[XLEN:2*XLEN-1]
43 Special Registers Altered:
47 # [DRAFT] Divide/Modulo Double-width Doubleword Unsigned
51 * divmod2du RT,RA,RB,RC
55 <!-- SVP64: RA,RB,RC,RT have EXTRA2, RS as below
56 <!-- bit 8 of EXTRA is set : RS.[s|v]=RT.[s|v]+MAXVL
57 <!-- bit 8 of EXTRA is clear: RS.[s|v]=RC.[s|v]
58 if ((RC) <u (RB)) & ((RB) != [0]*XLEN) then
59 dividend[0:(XLEN*2)-1] <- (RC) || (RA)
60 divisor[0:(XLEN*2)-1] <- [0]*XLEN || (RB)
61 result <- dividend / divisor
62 modulo <- dividend % divisor
63 RT <- result[XLEN:(XLEN*2)-1]
64 RS <- modulo[XLEN:(XLEN*2)-1]
71 Special Registers Altered:
75 # [DRAFT] Double-width Shift Left Doubleword
79 * dsld RT,RA,RB,RC (Rc=0)
80 * dsld. RT,RA,RB,RC (Rc=1)
87 RT <- (v[0:63] & mask) | ((RC) & ¬mask)
89 overflow <- 0 # relevant only when Rc=1
91 overflow <- 1 # relevant only when Rc=1
93 Special Registers Altered:
97 # [DRAFT] Double-width Shift Right Doubleword
101 * dsrd RT,RA,RB,RC (Rc=0)
102 * dsrd. RT,RA,RB,RC (Rc=1)
107 v <- ROTL64((RA), 64-n)
109 RT <- (v[0:63] & mask) | ((RC) & ¬mask)
110 RS <- v[0:63] & ¬mask
111 overflow <- 0 # relevant only when Rc=1
113 overflow <- 1 # relevant only when Rc=1
115 Special Registers Altered: