1 # [DRAFT] Twin Multiply and Add Doubleword
9 <!-- SVP64: RA,RB,RC,RT have EXTRA2, RS as below
10 <!-- bit 8 of EXTRA is clear: RS.[s|v]=RT.[s|v]+MAXVL
11 <!-- bit 8 of EXTRA is set : RS.[s|v]=RC.[s|v]
12 prod[0:127] <- (RA) * (RB)
13 sum[0:127] <- EXTZ(RC) + prod
17 Special Registers Altered:
21 # [DRAFT] Twin Divide/Modulo Quad Unsigned
25 * divmod2du RT,RA,RB,RC
29 <!-- SVP64: RA,RB,RC,RT have EXTRA2, RS as below
30 <!-- bit 8 of EXTRA is clear: RS.[s|v]=RT.[s|v]+MAXVL
31 <!-- bit 8 of EXTRA is set : RS.[s|v]=RC.[s|v]
32 if ((RC) <u (RB)) & ((RB) != [0]*XLEN) then
33 dividend[0:(XLEN*2)-1] <- (RC) || (RA)
34 divisor[0:(XLEN*2)-1] <- [0]*XLEN || (RB)
35 result <- dividend / divisor
36 modulo <- dividend % divisor
37 RT <- result[XLEN:(XLEN*2)-1]
38 RS <- modulo[XLEN:(XLEN*2)-1]
45 Special Registers Altered: