openpower/isa/svfixedarith.mdwn

   1 # [DRAFT] Twin Multiply and Add Doubleword
   2
   3 VA-Form
   4
   5 * madded RT,RA,RB,RC
   6
   7 Pseudo-code:
   8
   9     <!-- SVP64: RA,RB,RC,RT have EXTRA2, RS as below
  10     <!-- bit 8 of EXTRA is clear: RS.[s|v]=RT.[s|v]+MAXVL
  11     <!-- bit 8 of EXTRA is set  : RS.[s|v]=RC.[s|v]
  12     prod[0:127] <- (RA) * (RB)
  13     sum[0:127] <- EXTZ(RC) + prod
  14     RT <- sum[64:127]
  15     RS <- sum[0:63]
  16
  17 Special Registers Altered:
  18
  19     None
  20
  21 # [DRAFT] Twin Divide/Modulo Quad Unsigned
  22
  23 VA-Form
  24
  25 * divmod2du   RT,RA,RB,RC
  26
  27 Pseudo-code:
  28
  29     <!-- SVP64: RA,RB,RC,RT have EXTRA2, RS as below
  30     <!-- bit 8 of EXTRA is clear: RS.[s|v]=RT.[s|v]+MAXVL
  31     <!-- bit 8 of EXTRA is set  : RS.[s|v]=RC.[s|v]
  32     if ((RC) <u (RB)) & ((RB) != [0]*XLEN) then
  33         dividend[0:(XLEN*2)-1] <- (RC) || (RA)
  34         divisor[0:(XLEN*2)-1] <- [0]*XLEN || (RB)
  35         result <- dividend / divisor
  36         modulo <- dividend % divisor
  37         RT <- result[XLEN:(XLEN*2)-1]
  38         RS <- modulo[XLEN:(XLEN*2)-1]
  39         overflow <- 0
  40     else
  41         overflow <- 1
  42         RT <- [1]*XLEN
  43         RS <- [0]*XLEN
  44
  45 Special Registers Altered:
  46
  47     None
  48
  49 # [DRAFT] Twin (Quad) Left Shift Doubleword
  50
  51 Z23-Form
  52
  53 * dsld   RT,RA,RB,sm  (Rc=0)
  54 * dsld.   RT,RA,RB,sm  (Rc=1)
  55
  56 Pseudo-code:
  57
  58     sh <- (RB)
  59     hi <- (RT)
  60     lo <- (RA)
  61     n <- sh[58:63]
  62     mask[0:63] <- MASK(0, 63 - n)
  63     v[0:63] <- (hi & mask) | (lo & ¬mask)
  64     RT <- ROTL64(v, n)
  65
  66 Special Registers Altered:
  67
  68     CR0                    (if Rc=1)