1 <!-- This defines SVP64 bit-reversed Load instructions -->
2 <!-- They are augmented variants of v3.0B Load instructions -->
3 <!-- and are designed specifically for Cooley-Tukey FFT/DCT -->
15 EA <- b + SHL64(bitrev(srcstep, VL) * EXTS(SVD), n)
16 RT <- [0]*56 || MEM(EA, 1)
18 Special Registers Altered:
22 # Load Byte and Zero with Update
26 * lbzubr RT,SVD(RA),RC
31 EA <- (RA) + SHL64(bitrev(srcstep, VL) * EXTS(SVD), n)
32 RT <- [0] * 56 || MEM(EA, 1)
35 Special Registers Altered:
39 # Load Halfword and Zero
49 EA <- b + SHL64(bitrev(srcstep, VL) * EXTS(SVD), n)
50 RT <- [0] * 48 || MEM(EA, 2)
52 Special Registers Altered:
56 # Load Halfword and Zero with Update
60 * lhzubr RT,SVD(RA),RC
65 EA <- (RA) + SHL64(bitrev(srcstep, VL) * EXTS(SVD), n)
66 RT <- [0] * 48 || MEM(EA, 2)
69 Special Registers Altered:
73 # Load Halfword Algebraic
83 EA <- b + SHL64(bitrev(srcstep, VL) * EXTS(SVD), n)
84 RT <- EXTS(MEM(EA, 2))
86 Special Registers Altered:
90 # Load Halfword Algebraic with Update
94 * lhaubr RT,SVD(RA),RC
99 EA <- (RA) + SHL64(bitrev(srcstep, VL) * EXTS(SVD), n)
100 RT <- EXTS(MEM(EA, 2))
103 Special Registers Altered:
111 * lwzbr RT,SVD(RA),RC
117 EA <- b + SHL64(bitrev(srcstep, VL) * EXTS(SVD), n)
118 RT <- [0] * 32 || MEM(EA, 4)
120 Special Registers Altered:
124 # Load Word and Zero with Update
128 * lwzubr RT,SVD(RA),RC
133 EA <- (RA) + SHL64(bitrev(srcstep, VL) * EXTS(SVD), n)
134 RT <- [0]*32 || MEM(EA, 4)
137 Special Registers Altered:
141 # Load Word Algebraic
145 * lwabr RT,SVDS(RA),RC
151 EA <- b + SHL64(bitrev(srcstep, VL) * EXTS(SVDS || 0b00), n)
152 RT <- EXTS(MEM(EA, 4))
154 Special Registers Altered:
162 * ldbr RT,SVDS(RA),RC
168 EA <- b + SHL64(bitrev(srcstep, VL) * EXTS(SVDS || 0b00), n)
171 Special Registers Altered:
175 # Load Doubleword with Update Indexed
179 * ldubr RT,SVDS(RA),RC
184 EA <- (RA) + SHL64(bitrev(srcstep, VL) * EXTS(SVDS || 0b00), n)
188 Special Registers Altered: