openpower/isa/svfixedload.mdwn

   1 <!-- This defines SVP64 Shifted Load instructions -->
   2 <!-- They are augmented variants of v3.0B Load instructions -->
   3 <!-- and are designed to help with Cooley-Tukey FFT/DCT -->
   4
   5 # Load Byte and Zero
   6
   7 SVD-Form
   8
   9 * lbzsh RT,SVD(RA),RC
  10
  11 Pseudo-code:
  12
  13     b <- (RA|0)
  14     n <- (RC)[58:63]
  15     EA <- b + SHL64(srcstep * EXTS(SVD), n)
  16     RT <- [0]*56 || MEM(EA, 1)
  17
  18 Special Registers Altered:
  19
  20     None
  21
  22 # Load Byte and Zero with Update
  23
  24 SVD-Form
  25
  26 * lbzush RT,SVD(RA),RC
  27
  28 Pseudo-code:
  29
  30     n <- (RC)[58:63]
  31     EA <- (RA) + SHL64(srcstep * EXTS(SVD), n)
  32     RT <- [0] * 56 || MEM(EA, 1)
  33     RA <- EA
  34
  35 Special Registers Altered:
  36
  37     None
  38
  39 # Load Halfword and Zero
  40
  41 SVD-Form
  42
  43 * lhzsh RT,SVD(RA),RC
  44
  45 Pseudo-code:
  46
  47     b <- (RA|0)
  48     n <- (RC)[58:63]
  49     EA <- b + SHL64(srcstep * EXTS(SVD), n)
  50     RT <- [0] * 48 || MEM(EA, 2)
  51
  52 Special Registers Altered:
  53
  54     None
  55
  56 # Load Halfword and Zero with Update
  57
  58 SVD-Form
  59
  60 * lhzush RT,SVD(RA),RC
  61
  62 Pseudo-code:
  63
  64     n <- (RC)[58:63]
  65     EA <- (RA) + SHL64(srcstep * EXTS(SVD), n)
  66     RT <- [0] * 48 || MEM(EA, 2)
  67     RA <- EA
  68
  69 Special Registers Altered:
  70
  71     None
  72
  73 # Load Halfword Algebraic
  74
  75 SVD-Form
  76
  77 * lhash RT,SVD(RA),RC
  78
  79 Pseudo-code:
  80
  81     b <- (RA|0)
  82     n <- (RC)[58:63]
  83     EA <- b + SHL64(srcstep * EXTS(SVD), n)
  84     RT <- EXTS(MEM(EA, 2))
  85
  86 Special Registers Altered:
  87
  88     None
  89
  90 # Load Halfword Algebraic with Update
  91
  92 SVD-Form
  93
  94 * lhaush RT,SVD(RA),RC
  95
  96 Pseudo-code:
  97
  98     n <- (RC)[58:63]
  99     EA <- (RA) + SHL64(srcstep * EXTS(SVD), n)
 100     RT <- EXTS(MEM(EA, 2))
 101     RA <- EA
 102
 103 Special Registers Altered:
 104
 105     None
 106
 107 # Load Word and Zero
 108
 109 SVD-Form
 110
 111 * lwzsh RT,SVD(RA),RC
 112
 113 Pseudo-code:
 114
 115     b <- (RA|0)
 116     n <- (RC)[58:63]
 117     EA <- b + SHL64(srcstep * EXTS(SVD), n)
 118     RT <- [0] * 32 || MEM(EA, 4)
 119
 120 Special Registers Altered:
 121
 122     None
 123
 124 # Load Word and Zero with Update
 125
 126 SVD-Form
 127
 128 * lwzush RT,SVD(RA),RC
 129
 130 Pseudo-code:
 131
 132     n <- (RC)[58:63]
 133     EA <- (RA) + SHL64(srcstep * EXTS(SVD), n)
 134     RT <- [0]*32 || MEM(EA, 4)
 135     RA <- EA
 136
 137 Special Registers Altered:
 138
 139     None
 140
 141 # Load Word Algebraic
 142
 143 SVDS-Form
 144
 145 * lwash RT,SVDS(RA),RC
 146
 147 Pseudo-code:
 148
 149     b <- (RA|0)
 150     n <- (RC)[58:63]
 151     EA <- b + SHL64(srcstep * EXTS(SVDS || 0b00), n)
 152     RT <- EXTS(MEM(EA, 4))
 153
 154 Special Registers Altered:
 155
 156     None
 157
 158 # Load Doubleword
 159
 160 SVDS-Form
 161
 162 * ldsh RT,SVDS(RA),RC
 163
 164 Pseudo-code:
 165
 166     b <- (RA|0)
 167     n <- (RC)[58:63]
 168     EA <- b + SHL64(srcstep * EXTS(SVDS || 0b00), n)
 169     RT <- MEM(EA, 8)
 170
 171 Special Registers Altered:
 172
 173     None
 174
 175 # Load Doubleword with Update Indexed
 176
 177 SVDS-Form
 178
 179 * ldush RT,SVDS(RA),RC
 180
 181 Pseudo-code:
 182
 183     n <- (RC)[58:63]
 184     EA <- (RA) + SHL64(srcstep * EXTS(SVDS || 0b00), n)
 185     RT <- MEM(EA, 8)
 186     RA <- EA
 187
 188 Special Registers Altered:
 189
 190     None
 191