1 <!-- SVP64 FP Instructions here described are based on -->
2 <!-- PowerISA Version 3.0 B Book 1 -->
4 <!-- FRS in each of these does not need to be explicitly declared -->
5 <!-- FRS is automatically calculated by SVP64 to FRT+VL (default elwidth) -->
6 <!-- (Vector FRS data sequentially starts immediately after FRT vectors) -->
8 # Floating Add FFT/DCT [Single]
12 * ffadds FRT,FRA,FRB (Rc=0)
13 * ffadds. FRT,FRA,FRB (Rc=1)
17 FRT <- FPADD32(FRA, FRB)
18 FRS <- FPSUB32(FRA, FRB)
20 Special Registers Altered:
27 # Floating Add FFT/DCT [Double]
31 * ffadd FRT,FRA,FRB (Rc=0)
32 * ffadd. FRT,FRA,FRB (Rc=1)
36 FRT <- FPADD64(FRA, FRB)
37 FRS <- FPSUB64(FRA, FRB)
39 Special Registers Altered:
46 # Floating Subtract FFT/DCT [Single]
50 * ffsubs FRT,FRA,FRB (Rc=0)
51 * ffsubs. FRT,FRA,FRB (Rc=1)
55 FRT <- FPSUB32(FRA, FRB)
56 FRS <- FPADD32(FRA, FRB)
58 Special Registers Altered:
65 # Floating Subtract FFT/DCT [Double]
69 * ffsub FRT,FRA,FRB (Rc=0)
70 * ffsub. FRT,FRA,FRB (Rc=1)
74 FRT <- FPSUB64(FRA, FRB)
75 FRS <- FPADD64(FRA, FRB)
77 Special Registers Altered:
84 # Floating Multiply FFT/DCT [Single]
88 * ffmuls FRT,FRA,FRC (Rc=0)
89 * ffmuls. FRT,FRA,FRC (Rc=1)
93 FRT <- FPMUL32(FRA, FRC)
94 FRS <- FPMUL32(FRA, FRC, -1)
96 Special Registers Altered:
103 # Floating Multiply FFT/DCT [Double]
107 * ffmul FRT,FRA,FRC (Rc=0)
108 * ffmul. FRT,FRA,FRC (Rc=1)
112 FRT <- FPMUL64(FRA, FRC)
113 FRS <- FPMUL64(FRA, FRC, -1)
115 Special Registers Altered:
122 # Floating Divide FFT/DCT [Single]
126 * ffdivs FRT,FRA,FRB (Rc=0)
127 * ffdivs. FRT,FRA,FRB (Rc=1)
131 FRT <- FPDIV32(FRA, FRB)
132 FRS <- FPDIV32(FRA, FRB, -1)
134 Special Registers Altered:
141 # Floating Divide FFT/DCT [Double]
145 * ffdiv FRT,FRA,FRB (Rc=0)
146 * ffdiv. FRT,FRA,FRB (Rc=1)
150 FRT <- FPDIV64(FRA, FRB)
151 FRS <- FPDIV64(FRA, FRB, -1)
153 Special Registers Altered:
160 # Floating Multiply-Add FFT/DCT [Single]
164 * ffmadds FRT,FRA,FRC,FRB (Rc=0)
165 * ffmadds. FRT,FRA,FRC,FRB (Rc=1)
169 FRT <- FPMULADD32(FRA, FRC, FRB, 1, 1)
170 FRS <- FPMULADD32(FRA, FRC, FRB, -1, 1)
172 Special Registers Altered:
179 # Floating Multiply-Sub FFT/DCT [Single]
183 * ffmsubs FRT,FRA,FRC,FRB (Rc=0)
184 * ffmsubs. FRT,FRA,FRC,FRB (Rc=1)
188 FRT <- FPMULADD32(FRA, FRC, FRA, 1, -1)
189 FRS <- FPMULADD32(FRA, FRC, FRB, -1, -1)
191 Special Registers Altered:
198 # Floating Negative Multiply-Add FFT/DCT [Single]
202 * ffnmadds FRT,FRA,FRC,FRB (Rc=0)
203 * ffnmadds. FRT,FRA,FRC,FRB (Rc=1)
207 FRT <- FPMULADD32(FRA, FRC, FRA, -1, -1)
208 FRS <- FPMULADD32(FRA, FRC, FRB, 1, -1)
210 Special Registers Altered:
217 # Floating Negative Multiply-Sub FFT/DCT [Single]
221 * ffnmsubs FRT,FRA,FRC,FRB (Rc=0)
222 * ffnmsubs. FRT,FRA,FRC,FRB (Rc=1)
226 FRT <- FPMULADD32(FRA, FRC, FRA, -1, 1)
227 FRS <- FPMULADD32(FRA, FRC, FRB, 1, 1)
229 Special Registers Altered: