openpower/isa/svfparith.mdwn

   1 <!-- SVP64 FP Instructions here described are based on -->
   2 <!--  PowerISA Version 3.0 B Book 1 -->
   3
   4 <!-- FRS in each of these does not need to be explicitly declared -->
   5 <!-- FRS is automatically calculated by SVP64 to FRT+VL (default elwidth) -->
   6 <!-- (Vector FRS data sequentially starts immediately after FRT vectors) -->
   7
   8 <!-- PLEASE NOTE THESE ARE UNAPPROVED AND DRAFT, NOT SUBMITTED TO OPF ISA WG -->
   9
  10 # [DRAFT] Floating Add FFT/DCT [Single]
  11
  12 A-Form
  13
  14 * ffadds FRT,FRA,FRB (Rc=0)
  15 * ffadds. FRT,FRA,FRB (Rc=1)
  16
  17 Pseudo-code:
  18
  19     FRT <- FPADD32(FRA, FRB)
  20     FRS <- FPSUB32(FRB, FRA)
  21
  22 Special Registers Altered:
  23
  24     FPRF FR FI
  25     FX OX UX XX
  26     VXSNAN VXISI
  27     CR1          (if Rc=1)
  28
  29 # [DRAFT] Floating Add FFT/DCT [Double]
  30
  31 A-Form
  32
  33 * ffadd FRT,FRA,FRB (Rc=0)
  34 * ffadd. FRT,FRA,FRB (Rc=1)
  35
  36 Pseudo-code:
  37
  38     FRT <- FPADD64(FRA, FRB)
  39     FRS <- FPSUB64(FRB, FRA)
  40
  41 Special Registers Altered:
  42
  43     FPRF FR FI
  44     FX OX UX XX
  45     VXSNAN VXISI
  46     CR1          (if Rc=1)
  47
  48 # [DRAFT] Floating Subtract FFT/DCT [Single]
  49
  50 A-Form
  51
  52 * ffsubs FRT,FRA,FRB (Rc=0)
  53 * ffsubs. FRT,FRA,FRB (Rc=1)
  54
  55 Pseudo-code:
  56
  57     FRT <- FPSUB32(FRB, FRA)
  58     FRS <- FPADD32(FRA, FRB)
  59
  60 Special Registers Altered:
  61
  62     FPRF FR FI
  63     FX OX UX XX
  64     VXSNAN VXISI
  65     CR1          (if Rc=1)
  66
  67 # [DRAFT] Floating Subtract FFT/DCT [Double]
  68
  69 A-Form
  70
  71 * ffsub FRT,FRA,FRB (Rc=0)
  72 * ffsub. FRT,FRA,FRB (Rc=1)
  73
  74 Pseudo-code:
  75
  76     FRT <- FPSUB64(FRB, FRA)
  77     FRS <- FPADD64(FRA, FRB)
  78
  79 Special Registers Altered:
  80
  81     FPRF FR FI
  82     FX OX UX XX
  83     VXSNAN VXISI
  84     CR1          (if Rc=1)
  85
  86 # [DRAFT] Floating Multiply FFT/DCT [Single]
  87
  88 A-Form
  89
  90 * ffmuls FRT,FRA,FRC (Rc=0)
  91 * ffmuls. FRT,FRA,FRC (Rc=1)
  92
  93 Pseudo-code:
  94
  95     FRT <- FPMUL32(FRA, FRC)
  96     FRS <- FPMUL32(FRA, FRC, -1)
  97
  98 Special Registers Altered:
  99
 100     FPRF FR FI
 101     FX OX UX XX
 102     VXSNAN VXISI
 103     CR1          (if Rc=1)
 104
 105 # [DRAFT] Floating Multiply FFT/DCT [Double]
 106
 107 A-Form
 108
 109 * ffmul FRT,FRA,FRC (Rc=0)
 110 * ffmul. FRT,FRA,FRC (Rc=1)
 111
 112 Pseudo-code:
 113
 114     FRT <- FPMUL64(FRA, FRC)
 115     FRS <- FPMUL64(FRA, FRC, -1)
 116
 117 Special Registers Altered:
 118
 119     FPRF FR FI
 120     FX OX UX XX
 121     VXSNAN VXISI
 122     CR1          (if Rc=1)
 123
 124 # [DRAFT] Floating Divide FFT/DCT [Single]
 125
 126 A-Form
 127
 128 * ffdivs FRT,FRA,FRB (Rc=0)
 129 * ffdivs. FRT,FRA,FRB (Rc=1)
 130
 131 Pseudo-code:
 132
 133     FRT <- FPDIV32(FRA, FRB)
 134     FRS <- FPDIV32(FRA, FRB, -1)
 135
 136 Special Registers Altered:
 137
 138     FPRF FR FI
 139     FX OX UX XX
 140     VXSNAN VXISI
 141     CR1          (if Rc=1)
 142
 143 # [DRAFT] Floating Divide FFT/DCT [Double]
 144
 145 A-Form
 146
 147 * ffdiv FRT,FRA,FRB (Rc=0)
 148 * ffdiv. FRT,FRA,FRB (Rc=1)
 149
 150 Pseudo-code:
 151
 152     FRT <- FPDIV64(FRA, FRB)
 153     FRS <- FPDIV64(FRA, FRB, -1)
 154
 155 Special Registers Altered:
 156
 157     FPRF FR FI
 158     FX OX UX XX
 159     VXSNAN VXISI
 160     CR1          (if Rc=1)
 161
 162 # [DRAFT] Floating Twin Multiply-Add DCT [Single]
 163
 164 A-Form
 165
 166 * fdmadds FRT,FRA,FRC,FRB (Rc=0)
 167 * fdmadds. FRT,FRA,FRC,FRB (Rc=1)
 168
 169 Pseudo-code:
 170
 171     FRS <- FPADD32(FRA, FRB)
 172     sub <- FPSUB32(FRA, FRB)
 173     FRT <- FPMUL32(FRC, sub)
 174
 175 Special Registers Altered:
 176
 177     FPRF FR FI
 178     FX OX UX XX
 179     VXSNAN VXISI VXIMZ
 180     CR1          (if Rc=1)
 181
 182 # [DRAFT] Floating Multiply-Add FFT [Single]
 183
 184 A-Form
 185
 186 * ffmadds FRT,FRA,FRC,FRB (Rc=0)
 187 * ffmadds. FRT,FRA,FRC,FRB (Rc=1)
 188
 189 Pseudo-code:
 190
 191     FRT <- FPMULADD32(FRA, FRC, FRB, 1, 1)
 192     FRS <- FPMULADD32(FRA, FRC, FRB, -1, 1)
 193
 194 Special Registers Altered:
 195
 196     FPRF FR FI
 197     FX OX UX XX
 198     VXSNAN VXISI VXIMZ
 199     CR1          (if Rc=1)
 200
 201 # [DRAFT] Floating Multiply-Sub FFT [Single]
 202
 203 A-Form
 204
 205 * ffmsubs FRT,FRA,FRC,FRB (Rc=0)
 206 * ffmsubs. FRT,FRA,FRC,FRB (Rc=1)
 207
 208 Pseudo-code:
 209
 210     FRT <- FPMULADD32(FRA, FRC, FRB, 1, -1)
 211     FRS <- FPMULADD32(FRA, FRC, FRB, -1, -1)
 212
 213 Special Registers Altered:
 214
 215     FPRF FR FI
 216     FX OX UX XX
 217     VXSNAN VXISI VXIMZ
 218     CR1          (if Rc=1)
 219
 220 # [DRAFT] Floating Negative Multiply-Add FFT [Single]
 221
 222 A-Form
 223
 224 * ffnmadds FRT,FRA,FRC,FRB (Rc=0)
 225 * ffnmadds. FRT,FRA,FRC,FRB (Rc=1)
 226
 227 Pseudo-code:
 228
 229     FRT <- FPMULADD32(FRA, FRC, FRB, -1, -1)
 230     FRS <- FPMULADD32(FRA, FRC, FRB, 1, -1)
 231
 232 Special Registers Altered:
 233
 234     FPRF FR FI
 235     FX OX UX XX
 236     VXSNAN VXISI VXIMZ
 237     CR1          (if Rc=1)
 238
 239 # [DRAFT] Floating Negative Multiply-Sub FFT [Single]
 240
 241 A-Form
 242
 243 * ffnmsubs FRT,FRA,FRC,FRB (Rc=0)
 244 * ffnmsubs. FRT,FRA,FRC,FRB (Rc=1)
 245
 246 Pseudo-code:
 247
 248     FRT <- FPMULADD32(FRA, FRC, FRB, -1, 1)
 249     FRS <- FPMULADD32(FRA, FRC, FRB, 1, 1)
 250
 251 Special Registers Altered:
 252
 253     FPRF FR FI
 254     FX OX UX XX
 255     VXSNAN VXISI VXIMZ
 256     CR1          (if Rc=1)