1 <!-- SVP64 FP Instructions here described are based on -->
2 <!-- PowerISA Version 3.0 B Book 1 -->
4 <!-- FRS in each of these does not need to be explicitly declared -->
5 <!-- FRS is automatically calculated by SVP64 to FRT+VL (default elwidth) -->
6 <!-- (Vector FRS data sequentially starts immediately after FRT vectors) -->
8 <!-- PLEASE NOTE THESE ARE UNAPPROVED AND DRAFT, NOT SUBMITTED TO OPF ISA WG -->
10 # [DRAFT] Floating Add FFT/DCT [Single]
14 * ffadds FRT,FRA,FRB (Rc=0)
15 * ffadds. FRT,FRA,FRB (Rc=1)
19 FRT <- FPADD32(FRA, FRB)
20 FRS <- FPSUB32(FRB, FRA)
22 Special Registers Altered:
29 # [DRAFT] Floating Add FFT/DCT [Double]
33 * ffadd FRT,FRA,FRB (Rc=0)
34 * ffadd. FRT,FRA,FRB (Rc=1)
38 FRT <- FPADD64(FRA, FRB)
39 FRS <- FPSUB64(FRB, FRA)
41 Special Registers Altered:
48 # [DRAFT] Floating Subtract FFT/DCT [Single]
52 * ffsubs FRT,FRA,FRB (Rc=0)
53 * ffsubs. FRT,FRA,FRB (Rc=1)
57 FRT <- FPSUB32(FRB, FRA)
58 FRS <- FPADD32(FRA, FRB)
60 Special Registers Altered:
67 # [DRAFT] Floating Subtract FFT/DCT [Double]
71 * ffsub FRT,FRA,FRB (Rc=0)
72 * ffsub. FRT,FRA,FRB (Rc=1)
76 FRT <- FPSUB64(FRB, FRA)
77 FRS <- FPADD64(FRA, FRB)
79 Special Registers Altered:
86 # [DRAFT] Floating Multiply FFT/DCT [Single]
90 * ffmuls FRT,FRA,FRC (Rc=0)
91 * ffmuls. FRT,FRA,FRC (Rc=1)
95 FRT <- FPMUL32(FRA, FRC)
96 FRS <- FPMUL32(FRA, FRC, -1)
98 Special Registers Altered:
105 # [DRAFT] Floating Multiply FFT/DCT [Double]
109 * ffmul FRT,FRA,FRC (Rc=0)
110 * ffmul. FRT,FRA,FRC (Rc=1)
114 FRT <- FPMUL64(FRA, FRC)
115 FRS <- FPMUL64(FRA, FRC, -1)
117 Special Registers Altered:
124 # [DRAFT] Floating Divide FFT/DCT [Single]
128 * ffdivs FRT,FRA,FRB (Rc=0)
129 * ffdivs. FRT,FRA,FRB (Rc=1)
133 FRT <- FPDIV32(FRA, FRB)
134 FRS <- FPDIV32(FRA, FRB, -1)
136 Special Registers Altered:
143 # [DRAFT] Floating Divide FFT/DCT [Double]
147 * ffdiv FRT,FRA,FRB (Rc=0)
148 * ffdiv. FRT,FRA,FRB (Rc=1)
152 FRT <- FPDIV64(FRA, FRB)
153 FRS <- FPDIV64(FRA, FRB, -1)
155 Special Registers Altered:
162 # [DRAFT] Floating Twin Multiply-Add DCT [Single]
166 * fdmadds FRT,FRA,FRB (Rc=0)
167 * fdmadds. FRT,FRA,FRB (Rc=1)
171 FRS <- FPADD32(FRT, FRB)
172 sub <- FPSUB32(FRT, FRB)
173 FRT <- FPMUL32(FRA, sub)
175 Special Registers Altered:
182 # [DRAFT] Floating Multiply-Add FFT [Single]
186 * ffmadds FRT,FRA,FRB (Rc=0)
187 * ffmadds. FRT,FRA,FRB (Rc=1)
192 FRT <- FPMULADD32(tmp, FRA, FRB, 1, 1)
193 FRS <- FPMULADD32(tmp, FRA, FRB, -1, 1)
195 Special Registers Altered:
202 # [DRAFT] Floating Multiply-Sub FFT [Single]
206 * ffmsubs FRT,FRA,FRB (Rc=0)
207 * ffmsubs. FRT,FRA,FRB (Rc=1)
212 FRT <- FPMULADD32(tmp, FRA, FRB, 1, -1)
213 FRS <- FPMULADD32(tmp, FRA, FRB, -1, -1)
215 Special Registers Altered:
222 # [DRAFT] Floating Negative Multiply-Add FFT [Single]
226 * ffnmadds FRT,FRA,FRB (Rc=0)
227 * ffnmadds. FRT,FRA,FRB (Rc=1)
232 FRT <- FPMULADD32(tmp, FRA, FRB, -1, -1)
233 FRS <- FPMULADD32(tmp, FRA, FRB, 1, -1)
235 Special Registers Altered:
242 # [DRAFT] Floating Negative Multiply-Sub FFT [Single]
246 * ffnmsubs FRT,FRA,FRB (Rc=0)
247 * ffnmsubs. FRT,FRA,FRB (Rc=1)
252 FRT <- FPMULADD32(tmp, FRA, FRB, -1, 1)
253 FRS <- FPMULADD32(tmp, FRA, FRB, 1, 1)
255 Special Registers Altered: