1 <!-- SVP64 FP Instructions here described are based on -->
2 <!-- PowerISA Version 3.0 B Book 1 -->
4 # Floating Add [Single]
8 * faddso FRT,FRA,FRB (Rc=0)
9 * faddso. FRT,FRA,FRB (Rc=1)
13 FRT <- FPADD32(FRA, FRB)
14 FRS <- FPSUB32(FRA, FRB)
16 Special Registers Altered:
23 # Floating Add [Double]
27 * faddo FRT,FRA,FRB (Rc=0)
28 * faddo. FRT,FRA,FRB (Rc=1)
32 FRT <- FPADD64(FRA, FRB)
33 FRS <- FPSUB64(FRA, FRB)
35 Special Registers Altered:
42 # Floating Subtract [Single]
46 * fsubso FRT,FRA,FRB (Rc=0)
47 * fsubso. FRT,FRA,FRB (Rc=1)
51 FRT <- FPSUB32(FRA, FRB)
52 FRS <- FPADD32(FRA, FRB)
54 Special Registers Altered:
61 # Floating Subtract [Double]
65 * fsubo FRT,FRA,FRB (Rc=0)
66 * fsubo. FRT,FRA,FRB (Rc=1)
70 FRT <- FPSUB64(FRA, FRB)
71 FRS <- FPADD64(FRA, FRB)
73 Special Registers Altered:
80 # Floating Multiply [Single]
84 * fmulso FRT,FRA,FRC (Rc=0)
85 * fmulso. FRT,FRA,FRC (Rc=1)
89 FRT <- FPMUL32(FRA, FRC)
90 FRS <- FPMUL32(FRA, FRC, -1)
92 Special Registers Altered:
99 # Floating Multiply [Double]
103 * fmulo FRT,FRA,FRC (Rc=0)
104 * fmulo. FRT,FRA,FRC (Rc=1)
108 FRT <- FPMUL64(FRA, FRC)
109 FRS <- FPMUL64(FRA, FRC, -1)
111 Special Registers Altered:
118 # Floating Divide [Single]
122 * fdivso FRT,FRA,FRB (Rc=0)
123 * fdivso. FRT,FRA,FRB (Rc=1)
127 FRT <- FPDIV32(FRA, FRB)
128 FRS <- FPDIV32(FRA, FRB, -1)
130 Special Registers Altered:
137 # Floating Divide [Double]
141 * fdivo FRT,FRA,FRB (Rc=0)
142 * fdivo. FRT,FRA,FRB (Rc=1)
146 FRT <- FPDIV64(FRA, FRB)
147 FRS <- FPDIV64(FRA, FRB, -1)
149 Special Registers Altered:
156 # Floating Multiply-Add [Single]
160 * fmaddso FRT,FRA,FRC,FRB (Rc=0)
161 * fmaddso. FRT,FRA,FRC,FRB (Rc=1)
165 FRT <- FPMULADD32(FRA, FRC, FRB, 1, 1)
166 FRS <- FPMULADD32(FRA, FRC, FRB, 1, -1)
168 Special Registers Altered:
175 # Floating Multiply-Sub [Single]
179 * fmsubso FRT,FRA,FRC,FRB (Rc=0)
180 * fmsubso. FRT,FRA,FRC,FRB (Rc=1)
184 FRT <- FPMULADD32(FRA, FRC, FRB, 1, -1)
185 FRS <- FPMULADD32(FRA, FRC, FRB, 1, 1)
187 Special Registers Altered:
194 # Floating Negative Multiply-Add [Single]
198 * fnmaddso FRT,FRA,FRC,FRB (Rc=0)
199 * fnmaddso. FRT,FRA,FRC,FRB (Rc=1)
203 FRT <- FPMULADD32(FRA, FRC, FRB, -1, -1)
204 FRS <- FPMULADD32(FRA, FRC, FRB, -1, 1)
206 Special Registers Altered:
213 # Floating Negative Multiply-Sub [Single]
217 * fnmsubso FRT,FRA,FRC,FRB (Rc=0)
218 * fnmsubso. FRT,FRA,FRC,FRB (Rc=1)
222 FRT <- FPMULADD32(FRA, FRC, FRB, -1, 1)
223 FRS <- FPMULADD32(FRA, FRC, FRB, -1, -1)
225 Special Registers Altered: