openpower/isa/svfparith.mdwn

   1 <!-- SVP64 FP Instructions here described are based on -->
   2 <!--  PowerISA Version 3.0 B Book 1 -->
   3
   4 # Floating Add FFT/DCT [Single]
   5
   6 A-Form
   7
   8 * faddso FRT,FRA,FRB (Rc=0)
   9 * faddso. FRT,FRA,FRB (Rc=1)
  10
  11 Pseudo-code:
  12
  13     FRT <- FPADD32(FRA, FRB)
  14     FRS <- FPSUB32(FRA, FRB)
  15
  16 Special Registers Altered:
  17
  18     FPRF FR FI
  19     FX OX UX XX
  20     VXSNAN VXISI
  21     CR1          (if Rc=1)
  22
  23 # Floating Add FFT/DCT [Double]
  24
  25 A-Form
  26
  27 * faddo FRT,FRA,FRB (Rc=0)
  28 * faddo. FRT,FRA,FRB (Rc=1)
  29
  30 Pseudo-code:
  31
  32     FRT <- FPADD64(FRA, FRB)
  33     FRS <- FPSUB64(FRA, FRB)
  34
  35 Special Registers Altered:
  36
  37     FPRF FR FI
  38     FX OX UX XX
  39     VXSNAN VXISI
  40     CR1          (if Rc=1)
  41
  42 # Floating Subtract FFT/DCT [Single]
  43
  44 A-Form
  45
  46 * fsubso FRT,FRA,FRB (Rc=0)
  47 * fsubso. FRT,FRA,FRB (Rc=1)
  48
  49 Pseudo-code:
  50
  51     FRT <- FPSUB32(FRA, FRB)
  52     FRS <- FPADD32(FRA, FRB)
  53
  54 Special Registers Altered:
  55
  56     FPRF FR FI
  57     FX OX UX XX
  58     VXSNAN VXISI
  59     CR1          (if Rc=1)
  60
  61 # Floating Subtract FFT/DCT [Double]
  62
  63 A-Form
  64
  65 * fsubo FRT,FRA,FRB (Rc=0)
  66 * fsubo. FRT,FRA,FRB (Rc=1)
  67
  68 Pseudo-code:
  69
  70     FRT <- FPSUB64(FRA, FRB)
  71     FRS <- FPADD64(FRA, FRB)
  72
  73 Special Registers Altered:
  74
  75     FPRF FR FI
  76     FX OX UX XX
  77     VXSNAN VXISI
  78     CR1          (if Rc=1)
  79
  80 # Floating Multiply FFT/DCT [Single]
  81
  82 A-Form
  83
  84 * fmulso FRT,FRA,FRC (Rc=0)
  85 * fmulso. FRT,FRA,FRC (Rc=1)
  86
  87 Pseudo-code:
  88
  89     FRT <- FPMUL32(FRA, FRC)
  90     FRS <- FPMUL32(FRA, FRC, -1)
  91
  92 Special Registers Altered:
  93
  94     FPRF FR FI
  95     FX OX UX XX
  96     VXSNAN VXISI
  97     CR1          (if Rc=1)
  98
  99 # Floating Multiply FFT/DCT [Double]
 100
 101 A-Form
 102
 103 * fmulo FRT,FRA,FRC (Rc=0)
 104 * fmulo. FRT,FRA,FRC (Rc=1)
 105
 106 Pseudo-code:
 107
 108     FRT <- FPMUL64(FRA, FRC)
 109     FRS <- FPMUL64(FRA, FRC, -1)
 110
 111 Special Registers Altered:
 112
 113     FPRF FR FI
 114     FX OX UX XX
 115     VXSNAN VXISI
 116     CR1          (if Rc=1)
 117
 118 # Floating Divide FFT/DCT [Single]
 119
 120 A-Form
 121
 122 * fdivso FRT,FRA,FRB (Rc=0)
 123 * fdivso. FRT,FRA,FRB (Rc=1)
 124
 125 Pseudo-code:
 126
 127     FRT <- FPDIV32(FRA, FRB)
 128     FRS <- FPDIV32(FRA, FRB, -1)
 129
 130 Special Registers Altered:
 131
 132     FPRF FR FI
 133     FX OX UX XX
 134     VXSNAN VXISI
 135     CR1          (if Rc=1)
 136
 137 # Floating Divide FFT/DCT [Double]
 138
 139 A-Form
 140
 141 * fdivo FRT,FRA,FRB (Rc=0)
 142 * fdivo. FRT,FRA,FRB (Rc=1)
 143
 144 Pseudo-code:
 145
 146     FRT <- FPDIV64(FRA, FRB)
 147     FRS <- FPDIV64(FRA, FRB, -1)
 148
 149 Special Registers Altered:
 150
 151     FPRF FR FI
 152     FX OX UX XX
 153     VXSNAN VXISI
 154     CR1          (if Rc=1)
 155
 156 # Floating Multiply-Add FFT/DCT [Single]
 157
 158 A-Form
 159
 160 * fmaddso FRT,FRA,FRC,FRB (Rc=0)
 161 * fmaddso. FRT,FRA,FRC,FRB (Rc=1)
 162
 163 Pseudo-code:
 164
 165     FRT <- FPMULADD32(FRA, FRC, FRB, 1, 1)
 166     FRS <- FPMULADD32(FRA, FRC, FRB, 1, -1)
 167
 168 Special Registers Altered:
 169
 170     FPRF FR FI
 171     FX OX UX XX
 172     VXSNAN VXISI VXIMZ
 173     CR1          (if Rc=1)
 174
 175 # Floating Multiply-Sub FFT/DCT [Single]
 176
 177 A-Form
 178
 179 * fmsubso FRT,FRA,FRC,FRB (Rc=0)
 180 * fmsubso. FRT,FRA,FRC,FRB (Rc=1)
 181
 182 Pseudo-code:
 183
 184     FRT <- FPMULADD32(FRA, FRC, FRB, 1, -1)
 185     FRS <- FPMULADD32(FRA, FRC, FRB, 1, 1)
 186
 187 Special Registers Altered:
 188
 189     FPRF FR FI
 190     FX OX UX XX
 191     VXSNAN VXISI VXIMZ
 192     CR1          (if Rc=1)
 193
 194 # Floating Negative Multiply-Add FFT/DCT [Single]
 195
 196 A-Form
 197
 198 * fnmaddso FRT,FRA,FRC,FRB (Rc=0)
 199 * fnmaddso. FRT,FRA,FRC,FRB (Rc=1)
 200
 201 Pseudo-code:
 202
 203     FRT <- FPMULADD32(FRA, FRC, FRB, -1, -1)
 204     FRS <- FPMULADD32(FRA, FRC, FRB, -1, 1)
 205
 206 Special Registers Altered:
 207
 208     FPRF FR FI
 209     FX OX UX XX
 210     VXSNAN VXISI VXIMZ
 211     CR1          (if Rc=1)
 212
 213 # Floating Negative Multiply-Sub FFT/DCT [Single]
 214
 215 A-Form
 216
 217 * fnmsubso FRT,FRA,FRC,FRB (Rc=0)
 218 * fnmsubso. FRT,FRA,FRC,FRB (Rc=1)
 219
 220 Pseudo-code:
 221
 222     FRT <- FPMULADD32(FRA, FRC, FRB, -1, 1)
 223     FRS <- FPMULADD32(FRA, FRC, FRB, -1, -1)
 224
 225 Special Registers Altered:
 226
 227     FPRF FR FI
 228     FX OX UX XX
 229     VXSNAN VXISI VXIMZ
 230     CR1          (if Rc=1)
 231