1 <!-- SVP64 FP Instructions here described are based on -->
2 <!-- PowerISA Version 3.0 B Book 1 -->
4 <!-- FRS in each of these does not need to be explicitly declared -->
5 <!-- FRS is automatically calculated by SVP64 to FRT+VL (default elwidth) -->
6 <!-- (Vector FRS data sequentially starts immediately after FRT vectors) -->
8 <!-- PLEASE NOTE THESE ARE UNAPPROVED AND DRAFT, NOT SUBMITTED TO OPF ISA WG -->
10 # Floating Add FFT/DCT [Single]
14 * ffadds FRT,FRA,FRB (Rc=0)
15 * ffadds. FRT,FRA,FRB (Rc=1)
19 FRT <- FPADD32(FRA, FRB)
20 FRS <- FPSUB32(FRB, FRA)
22 Special Registers Altered:
29 # Floating Add FFT/DCT [Double]
33 * ffadd FRT,FRA,FRB (Rc=0)
34 * ffadd. FRT,FRA,FRB (Rc=1)
38 FRT <- FPADD64(FRA, FRB)
39 FRS <- FPSUB64(FRB, FRA)
41 Special Registers Altered:
48 # Floating Subtract FFT/DCT [Single]
52 * ffsubs FRT,FRA,FRB (Rc=0)
53 * ffsubs. FRT,FRA,FRB (Rc=1)
57 FRT <- FPSUB32(FRB, FRA)
58 FRS <- FPADD32(FRA, FRB)
60 Special Registers Altered:
67 # Floating Subtract FFT/DCT [Double]
71 * ffsub FRT,FRA,FRB (Rc=0)
72 * ffsub. FRT,FRA,FRB (Rc=1)
76 FRT <- FPSUB64(FRB, FRA)
77 FRS <- FPADD64(FRA, FRB)
79 Special Registers Altered:
86 # Floating Multiply FFT/DCT [Single]
90 * ffmuls FRT,FRA,FRC (Rc=0)
91 * ffmuls. FRT,FRA,FRC (Rc=1)
95 FRT <- FPMUL32(FRA, FRC)
96 FRS <- FPMUL32(FRA, FRC, -1)
98 Special Registers Altered:
105 # Floating Multiply FFT/DCT [Double]
109 * ffmul FRT,FRA,FRC (Rc=0)
110 * ffmul. FRT,FRA,FRC (Rc=1)
114 FRT <- FPMUL64(FRA, FRC)
115 FRS <- FPMUL64(FRA, FRC, -1)
117 Special Registers Altered:
124 # Floating Divide FFT/DCT [Single]
128 * ffdivs FRT,FRA,FRB (Rc=0)
129 * ffdivs. FRT,FRA,FRB (Rc=1)
133 FRT <- FPDIV32(FRA, FRB)
134 FRS <- FPDIV32(FRA, FRB, -1)
136 Special Registers Altered:
143 # Floating Divide FFT/DCT [Double]
147 * ffdiv FRT,FRA,FRB (Rc=0)
148 * ffdiv. FRT,FRA,FRB (Rc=1)
152 FRT <- FPDIV64(FRA, FRB)
153 FRS <- FPDIV64(FRA, FRB, -1)
155 Special Registers Altered:
162 # Floating Twin Multiply-Add DCT [Single]
166 * fdmadds FRT,FRA,FRC,FRB (Rc=0)
167 * fdmadds. FRT,FRA,FRC,FRB (Rc=1)
171 FRT <- FPADD32(FRA, FRB)
172 sub <- FPSUB32(FRB, FRA)
173 FRS <- FPMUL32(FRC, sub)
175 Special Registers Altered:
182 # Floating Multiply-Add FFT [Single]
186 * ffmadds FRT,FRA,FRC,FRB (Rc=0)
187 * ffmadds. FRT,FRA,FRC,FRB (Rc=1)
191 FRT <- FPMULADD32(FRA, FRC, FRB, 1, 1)
192 FRS <- FPMULADD32(FRA, FRC, FRB, -1, 1)
194 Special Registers Altered:
201 # Floating Multiply-Sub FFT [Single]
205 * ffmsubs FRT,FRA,FRC,FRB (Rc=0)
206 * ffmsubs. FRT,FRA,FRC,FRB (Rc=1)
210 FRT <- FPMULADD32(FRA, FRC, FRB, 1, -1)
211 FRS <- FPMULADD32(FRA, FRC, FRB, -1, -1)
213 Special Registers Altered:
220 # Floating Negative Multiply-Add FFT [Single]
224 * ffnmadds FRT,FRA,FRC,FRB (Rc=0)
225 * ffnmadds. FRT,FRA,FRC,FRB (Rc=1)
229 FRT <- FPMULADD32(FRA, FRC, FRB, -1, -1)
230 FRS <- FPMULADD32(FRA, FRC, FRB, 1, -1)
232 Special Registers Altered:
239 # Floating Negative Multiply-Sub FFT [Single]
243 * ffnmsubs FRT,FRA,FRC,FRB (Rc=0)
244 * ffnmsubs. FRT,FRA,FRC,FRB (Rc=1)
248 FRT <- FPMULADD32(FRA, FRC, FRB, -1, 1)
249 FRS <- FPMULADD32(FRA, FRC, FRB, 1, 1)
251 Special Registers Altered:
258 # Floating SIN [Single]
262 * fsins FRT,FRB (Rc=0)
263 * fsins. FRT,FRB (Rc=1)
269 Special Registers Altered:
276 # Floating COS [Single]
280 * fcoss FRT,FRB (Rc=0)
281 * fcoss. FRT,FRB (Rc=1)
287 Special Registers Altered: