added missing RA RB RT to TLI-Form fields.txt
[openpower-isa.git] / openpower / isatables / major.csv
1 opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form,CONDITIONS
2 12,ALU,OP_ADD,RA,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,1,NONE,0,0,0,0,0,0,NONE,0,0,addic,D,
3 13,ALU,OP_ADD,RA,CONST_SI,NONE,RT,NONE,CR0,0,0,ZERO,1,NONE,0,0,0,0,0,0,ONE,0,0,addic.,D,
4 14,ALU,OP_ADD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,addi,D,
5 15,ALU,OP_ADD,RA_OR_ZERO,CONST_SI_HI,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,addis,D,
6 17,TRAP,OP_SC,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,sc,SC,
7 28,LOGICAL,OP_AND,RS,CONST_UI,NONE,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,ONE,0,0,andi.,D,
8 29,LOGICAL,OP_AND,RS,CONST_UI_HI,NONE,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,ONE,0,0,andis.,D,
9 18,BRANCH,OP_B,NONE,CONST_LI,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,1,0,b,I,
10 16,BRANCH,OP_BC,SPR,CONST_BD,NONE,SPR,BI,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,1,0,bc,B,
11 11,ALU,OP_CMP,RA,CONST_SI,NONE,NONE,NONE,BF,1,0,ONE,0,NONE,0,0,0,0,0,1,NONE,0,0,cmpi,D,
12 10,ALU,OP_CMP,RA,CONST_UI,NONE,NONE,NONE,BF,1,0,ONE,0,NONE,0,0,0,0,0,0,NONE,0,0,cmpli,D,
13 34,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is1B,0,0,0,0,0,0,NONE,0,1,lbz,D,
14 35,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is1B,0,0,1,0,0,0,NONE,0,1,lbzu,D,
15 50,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,FRT,NONE,NONE,0,0,ZERO,0,is8B,0,0,0,0,0,0,NONE,0,1,lfd,D,
16 51,LDST,OP_LOAD,RA,CONST_SI,NONE,FRT,NONE,NONE,0,0,ZERO,0,is8B,0,0,1,0,0,0,NONE,0,1,lfdu,D,
17 48,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,FRT,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,1,0,NONE,0,1,lfs,D,
18 49,LDST,OP_LOAD,RA,CONST_SI,NONE,FRT,NONE,NONE,0,0,ZERO,0,is4B,0,0,1,0,1,0,NONE,0,1,lfsu,D,
19 42,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,1,0,0,0,0,NONE,0,1,lha,D,
20 43,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,1,1,0,0,0,NONE,0,1,lhau,D,
21 40,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,0,0,0,0,0,NONE,0,1,lhz,D,
22 41,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,0,1,0,0,0,NONE,0,1,lhzu,D,
23 32,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,0,0,NONE,0,1,lwz,D,
24 33,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is4B,0,0,1,0,0,0,NONE,0,1,lwzu,D,
25 7,MUL,OP_MUL_L64,RA,CONST_SI,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,1,NONE,0,0,mulli,D,
26 24,LOGICAL,OP_OR,RS,CONST_UI,NONE,RA,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,ori,D,
27 25,LOGICAL,OP_OR,RS,CONST_UI_HI,NONE,RA,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,oris,D,
28 20,SHIFT_ROT,OP_RLC,RA,CONST_SH32,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,rlwimi,M,
29 21,SHIFT_ROT,OP_RLC,NONE,CONST_SH32,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,rlwinm,M,
30 23,SHIFT_ROT,OP_RLC,NONE,RB,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,rlwnm,M,
31 38,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,NONE,NONE,0,0,ZERO,0,is1B,0,0,0,0,0,0,NONE,0,1,stb,D,
32 39,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,NONE,NONE,0,0,ZERO,0,is1B,0,0,1,0,0,0,NONE,0,1,stbu,D,
33 54,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,FRS,NONE,NONE,NONE,0,0,ZERO,0,is8B,0,0,0,0,0,0,NONE,0,1,stfd,D,
34 55,LDST,OP_STORE,RA,CONST_SI,FRS,NONE,NONE,NONE,0,0,ZERO,0,is8B,0,0,1,0,0,0,NONE,0,1,stfdu,D,
35 52,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,FRS,NONE,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,1,0,NONE,0,1,stfs,D,
36 53,LDST,OP_STORE,RA,CONST_SI,FRS,NONE,NONE,NONE,0,0,ZERO,0,is4B,0,0,1,0,1,0,NONE,0,1,stfsu,D,
37 44,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,NONE,NONE,0,0,ZERO,0,is2B,0,0,0,0,0,0,NONE,0,1,sth,D,
38 45,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,NONE,NONE,0,0,ZERO,0,is2B,0,0,1,0,0,0,NONE,0,1,sthu,D,
39 36,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,0,0,NONE,0,1,stw,D,
40 37,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,NONE,NONE,0,0,ZERO,0,is4B,0,0,1,0,0,0,NONE,0,1,stwu,D,
41 8,ALU,OP_ADD,RA,CONST_SI,NONE,RT,NONE,NONE,1,0,ONE,1,NONE,0,0,0,0,0,0,NONE,0,0,subfic,D,
42 2,TRAP,OP_TRAP,RA,CONST_SI,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,tdi,D,
43 3,TRAP,OP_TRAP,RA,CONST_SI,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,1,twi,D,
44 26,LOGICAL,OP_XOR,RS,CONST_UI,NONE,RA,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,xori,D,
45 27,LOGICAL,OP_XOR,RS,CONST_UI_HI,NONE,RA,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,xoris,D,