platforms/kc705.py

   1 from mibuild.generic_platform import *
   2 from mibuild.crg import SimpleCRG
   3 from mibuild.xilinx_common import CRG_DS
   4 from mibuild.xilinx_ise import XilinxISEPlatform
   5 from mibuild.xilinx_vivado import XilinxVivadoPlatform
   6 from mibuild.programmer import *
   7
   8 def _run_vivado(cmds):
   9         with subprocess.Popen("vivado -mode tcl", stdin=subprocess.PIPE, shell=True) as process:
  10                 process.stdin.write(cmds.encode("ASCII"))
  11                 process.communicate()
  12
  13 class VivadoProgrammer(Programmer):
  14         needs_bitreverse = False
  15
  16         def load_bitstream(self, bitstream_file):
  17                 cmds = """open_hw
  18 connect_hw_server
  19 open_hw_target [lindex [get_hw_targets -of_objects [get_hw_servers localhost]] 0]
  20
  21 set_property PROBES.FILE {{}} [lindex [get_hw_devices] 0]
  22 set_property PROGRAM.FILE {{{bitstream}}} [lindex [get_hw_devices] 0]
  23
  24 program_hw_devices [lindex [get_hw_devices] 0]
  25 refresh_hw_device [lindex [get_hw_devices] 0]
  26
  27 quit
  28 """.format(bitstream=bitstream_file)
  29                 _run_vivado(cmds)
  30
  31         def flash(self, address, data_file):
  32                 raise NotImplementedError
  33
  34 _io = [
  35         ("user_led", 0, Pins("AB8"), IOStandard("LVCMOS15")),
  36         ("user_led", 1, Pins("AA8"), IOStandard("LVCMOS15")),
  37         ("user_led", 2, Pins("AC9"), IOStandard("LVCMOS15")),
  38         ("user_led", 3, Pins("AB9"), IOStandard("LVCMOS15")),
  39         ("user_led", 4, Pins("AE26"), IOStandard("LVCMOS25")),
  40         ("user_led", 5, Pins("G19"), IOStandard("LVCMOS25")),
  41         ("user_led", 6, Pins("E18"), IOStandard("LVCMOS25")),
  42         ("user_led", 7, Pins("F16"), IOStandard("LVCMOS25")),
  43
  44         ("cpu_reset", 0, Pins("AB7"), IOStandard("LVCMOS15")),
  45
  46         ("clk200", 0,
  47                 Subsignal("p", Pins("AD12"), IOStandard("LVDS")),
  48                 Subsignal("n", Pins("AD11"), IOStandard("LVDS"))
  49         ),
  50
  51         ("clk156", 0,
  52                 Subsignal("p", Pins("K28"), IOStandard("LVDS_25")),
  53                 Subsignal("n", Pins("K29"), IOStandard("LVDS_25"))
  54         ),
  55
  56
  57         ("serial", 0,
  58                 Subsignal("cts", Pins("L27")),
  59                 Subsignal("rts", Pins("K23")),
  60                 Subsignal("tx", Pins("K24")),
  61                 Subsignal("rx", Pins("M19")),
  62                 IOStandard("LVCMOS25")
  63         ),
  64
  65         ("sata", 0,
  66                 Subsignal("refclk_p", Pins("C8")),
  67                 Subsignal("refclk_n", Pins("C7")),
  68                 Subsignal("txp", Pins("D2")),
  69                 Subsignal("txn", Pins("D1")),
  70                 Subsignal("rxp", Pins("E4")),
  71                 Subsignal("rxn", Pins("E3")),
  72         ),
  73 ]
  74
  75 def Platform(*args, toolchain="vivado", programmer="xc3sprog", **kwargs):
  76         if toolchain == "ise":
  77                 xilinx_platform = XilinxISEPlatform
  78         elif toolchain == "vivado":
  79                 xilinx_platform = XilinxVivadoPlatform
  80         else:
  81                 raise ValueError
  82
  83         class RealPlatform(xilinx_platform):
  84                 bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g ConfigRate:12 -g SPI_buswidth:4"
  85
  86                 def __init__(self, crg_factory=lambda p: CRG_DS(p, "clk200", "cpu_reset")):
  87                         xilinx_platform.__init__(self, "xc7k325t-ffg900-2", _io, crg_factory)
  88
  89                 def create_programmer(self):
  90                         if programmer == "xc3sprog":
  91                                 return XC3SProg("jtaghs1_fast", "bscan_spi_kc705.bit")
  92                         elif programmer == "vivado":
  93                                 return VivadoProgrammer()
  94                         else:
  95                                 raise ValueError
  96
  97                 def do_finalize(self, fragment):
  98                         try:
  99                                 self.add_period_constraint(self.lookup_request("clk156").p, 6.4)
 100                         except ConstraintError:
 101                                 pass
 102                         try:
 103                                 self.add_period_constraint(self.lookup_request("clk200").p, 5.0)
 104                         except ConstraintError:
 105                                 pass
 106                         try:
 107                                 self.add_period_constraint(self.lookup_request("sata_host").refclk_p, 6.66)
 108                         except ConstraintError:
 109                                 pass
 110                         self.add_platform_command("""
 111 create_clock -name sys_clk -period 6 [get_nets sys_clk]
 112 create_clock -name sata_rx_clk -period 3.33 [get_nets sata_rx_clk]
 113 create_clock -name sata_tx_clk -period 3.33 [get_nets sata_tx_clk]
 114
 115 set_false_path -from [get_clocks sys_clk] -to [get_clocks sata_rx_clk]
 116 set_false_path -from [get_clocks sys_clk] -to [get_clocks sata_tx_clk]
 117 set_false_path -from [get_clocks sata_rx_clk] -to [get_clocks sys_clk]
 118 set_false_path -from [get_clocks sata_tx_clk] -to [get_clocks sys_clk]
 119
 120 set_property CFGBVS VCCO [current_design]
 121 set_property CONFIG_VOLTAGE 2.5 [current_design]
 122 """)
 123
 124         return RealPlatform(*args, **kwargs)