setup: include software and Verilog files
[litex.git] / setup.py
1 #!/usr/bin/env python3
2
3 import sys
4 from setuptools import setup
5 from setuptools import find_packages
6
7
8 if sys.version_info[:3] < (3, 3):
9 raise SystemExit("You need Python 3.3+")
10
11
12 setup(
13 name="misoc",
14 version="1.0",
15 description="a high performance and small footprint SoC based on Migen",
16 long_description=open("README").read(),
17 author="Sebastien Bourdeauducq",
18 author_email="sb@m-labs.hk",
19 url="http://m-labs.hk",
20 download_url="https://github.com/m-labs/misoc",
21 license="BSD",
22 platforms=["Any"],
23 keywords="HDL ASIC FPGA hardware design",
24 classifiers=[
25 "Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)",
26 "Environment :: Console",
27 "Development Status :: Alpha",
28 "Intended Audience :: Developers",
29 "License :: OSI Approved :: BSD License",
30 "Operating System :: OS Independent",
31 "Programming Language :: Python",
32 ],
33 packages=find_packages(),
34 include_package_data=True,
35 entry_points={
36 "console_scripts": [
37 "flterm=misoc.tools.flterm:main",
38 "mkmscimg=misoc.tools.mkmscimg:main",
39 ],
40 },
41 )