simsoc.ys

   1 # rad the main peripheral fabric, then uart16550, and finally libresoc core
   2 # we do not have to do include the micron ddr3 model or the lattice ecp5
   3 # models because apparently they're good to go, already (icarus is a lot
   4 # stricter than verilator, hence the munging below)
   5
   6 read_ilang build_simsoc/top.il
   7 read_verilog  ../uart16550/rtl/verilog/raminfr.v
   8 read_verilog  ../uart16550/rtl/verilog/uart_defines.v
   9 read_verilog  ../uart16550/rtl/verilog/uart_rfifo.v
  10 read_verilog  ../uart16550/rtl/verilog/uart_top.v
  11 read_verilog  ../uart16550/rtl/verilog/timescale.v
  12 read_verilog  ../uart16550/rtl/verilog/uart_sync_flops.v
  13 read_verilog  ../uart16550/rtl/verilog/uart_debug_if.v
  14 read_verilog  ../uart16550/rtl/verilog/uart_regs.v
  15 read_verilog  ../uart16550/rtl/verilog/uart_transmitter.v
  16 read_verilog  ../uart16550/rtl/verilog/uart_receiver.v
  17 read_verilog  ../uart16550/rtl/verilog/uart_tfifo.v
  18 read_verilog  ../uart16550/rtl/verilog/uart_wb.v
  19 read_verilog  ../tercel-qspi/tercel/phy.v
  20 read_verilog  ../tercel-qspi/tercel/wishbone_spi_master.v
  21 # errors in the ethmac rtl, comment out for now
  22 #read_verilog  ../ethmac/rtl/verilog/eth_clockgen.v
  23 #read_verilog  ../ethmac/rtl/verilog/eth_cop.v
  24 #read_verilog  ../ethmac/rtl/verilog/eth_crc.v
  25 #read_verilog  ../ethmac/rtl/verilog/eth_fifo.v
  26 #read_verilog  ../ethmac/rtl/verilog/eth_maccontrol.v
  27 #read_verilog  ../ethmac/rtl/verilog/ethmac_defines.v
  28 #read_verilog  ../ethmac/rtl/verilog/eth_macstatus.v
  29 #read_verilog  ../ethmac/rtl/verilog/ethmac.v
  30 #read_verilog  ../ethmac/rtl/verilog/eth_miim.v
  31 #read_verilog  ../ethmac/rtl/verilog/eth_outputcontrol.v
  32 #read_verilog  ../ethmac/rtl/verilog/eth_random.v
  33 #read_verilog  ../ethmac/rtl/verilog/eth_receivecontrol.v
  34 #read_verilog  ../ethmac/rtl/verilog/eth_registers.v
  35 #read_verilog  ../ethmac/rtl/verilog/eth_register.v
  36 #read_verilog  ../ethmac/rtl/verilog/eth_rxaddrcheck.v
  37 #read_verilog  ../ethmac/rtl/verilog/eth_rxcounters.v
  38 #read_verilog  ../ethmac/rtl/verilog/eth_rxethmac.v
  39 #read_verilog  ../ethmac/rtl/verilog/eth_rxstatem.v
  40 #read_verilog  ../ethmac/rtl/verilog/eth_shiftreg.v
  41 #read_verilog  ../ethmac/rtl/verilog/eth_spram_256x32.v
  42 #read_verilog  ../ethmac/rtl/verilog/eth_top.v
  43 #read_verilog  ../ethmac/rtl/verilog/eth_transmitcontrol.v
  44 #read_verilog  ../ethmac/rtl/verilog/eth_txcounters.v
  45 #read_verilog  ../ethmac/rtl/verilog/eth_txethmac.v
  46 #read_verilog  ../ethmac/rtl/verilog/eth_txstatem.v
  47 #read_verilog  ../ethmac/rtl/verilog/eth_wishbone.v
  48 #read_verilog  ../ethmac/rtl/verilog/timescale.v
  49
  50 read_verilog  ./external_core_top.v
  51
  52 # stop yosys deleting stuff
  53 setattr -mod -set keep 1 uart_transmitter
  54 setattr -mod -set keep 1 uart_receiver
  55
  56 delete w:$verilog_initial_trigger
  57
  58 # these are most of "proc"
  59 proc_prune
  60 proc_clean
  61 proc_rmdead
  62 proc_init
  63 proc_arst
  64 proc_dlatch
  65 proc_dff
  66 proc_mux
  67 proc_rmdead
  68 proc_memwr
  69 proc_clean
  70 opt_expr -keepdc
  71
  72 # these are important to do in this order
  73 memory_collect
  74 pmuxtree
  75
  76 #opt_mem
  77 #opt_mem_priority
  78 #opt_mem_feedback
  79 #opt_clean
  80 extract_fa
  81 clean
  82 opt
  83 clean
  84 write_verilog -norename top.v
  85 stat