simsoc.ys

   1 read_ilang build/top.il
   2 read_verilog  ../uart16550/rtl/verilog/raminfr.v
   3 read_verilog  ../uart16550/rtl/verilog/uart_defines.v
   4 read_verilog  ../uart16550/rtl/verilog/uart_rfifo.v
   5 read_verilog  ../uart16550/rtl/verilog/uart_top.v
   6 read_verilog  ../uart16550/rtl/verilog/timescale.v
   7 read_verilog  ../uart16550/rtl/verilog/uart_sync_flops.v
   8 read_verilog  ../uart16550/rtl/verilog/uart_debug_if.v
   9 read_verilog  ../uart16550/rtl/verilog/uart_regs.v
  10 read_verilog  ../uart16550/rtl/verilog/uart_transmitter.v
  11 read_verilog  ../uart16550/rtl/verilog/uart_receiver.v
  12 read_verilog  ../uart16550/rtl/verilog/uart_tfifo.v
  13 read_verilog  ../uart16550/rtl/verilog/uart_wb.v
  14 read_verilog  ./external_core_top.v
  15
  16 setattr -mod -set keep 1 uart_transmitter
  17 setattr -mod -set keep 1 uart_receiver
  18
  19 delete w:$verilog_initial_trigger
  20 proc_prune
  21 proc_clean
  22 proc_rmdead
  23 proc_init
  24 proc_arst
  25 proc_dlatch
  26 proc_dff
  27 proc_mux
  28 proc_rmdead
  29 proc_memwr
  30 proc_clean
  31 opt_expr -keepdc
  32 memory_collect
  33 pmuxtree
  34 #opt_mem
  35 #opt_mem_priority
  36 #opt_mem_feedback
  37 #opt_clean
  38 extract_fa
  39 clean
  40 opt
  41 clean
  42 write_verilog -norename top.v
  43 stat