simulator/test_trap_sim.py

   1 from nmutil.formaltest import FHDLTestCase
   2 import unittest
   3 from openpower.simulator.program import Program
   4 from openpower.simulator.qemu import run_program
   5 from openpower.test.common import TestCase
   6 from openpower.simulator.test_sim import DecoderBase
   7 from openpower.endian import bigendian #XXX HACK!
   8
   9
  10 class TrapSimTestCases(FHDLTestCase):
  11     test_data = []
  12
  13     def __init__(self, name="div"):
  14         super().__init__(name)
  15         self.test_name = name
  16
  17     def test_0_not_twi(self):
  18         lst = ["addi 1, 0, 0x5678",
  19                "twi  4, 1, 0x5677",
  20                ]
  21         with Program(lst, bigendian) as program:
  22             self.run_tst_program(program, [1])
  23
  24     def test_1_twi_eq(self):
  25         lst = ["addi 1, 0, 0x5678",
  26                "twi  4, 1, 0x5678",
  27                ]
  28         with Program(lst, bigendian) as program:
  29             self.run_tst_program(program, [1])
  30
  31     def run_tst_program(self, prog, initial_regs=None, initial_sprs=None,
  32                                     initial_mem=None):
  33         initial_regs = [0] * 32
  34         tc = TestCase(prog, self.test_name, initial_regs, initial_sprs, 0,
  35                                             initial_mem, 0)
  36         self.test_data.append(tc)
  37
  38
  39 class TrapDecoderTestCase(DecoderBase, TrapSimTestCases):
  40     pass
  41
  42
  43 if __name__ == "__main__":
  44     unittest.main()