5 #include <hw/sdram_phy.h>
11 static void cdelay(int i
)
14 __asm__
volatile("nop");
21 dfii_control_write(DFII_CONTROL_CKE
);
22 printf("DDR now under software control\n");
27 dfii_control_write(DFII_CONTROL_SEL
|DFII_CONTROL_CKE
);
28 printf("DDR now under hardware control\n");
31 void ddrrow(char *_row
)
37 dfii_pi0_address_write(0x0000);
38 dfii_pi0_baddress_write(0);
39 command_p0(DFII_COMMAND_RAS
|DFII_COMMAND_WE
|DFII_COMMAND_CS
);
41 printf("Precharged\n");
43 row
= strtoul(_row
, &c
, 0);
45 printf("incorrect row\n");
48 dfii_pi0_address_write(row
);
49 dfii_pi0_baddress_write(0);
50 command_p0(DFII_COMMAND_RAS
|DFII_COMMAND_CS
);
52 printf("Activated row %d\n", row
);
56 void ddrrd(char *startaddr
)
63 printf("ddrrd <address>\n");
66 addr
= strtoul(startaddr
, &c
, 0);
68 printf("incorrect address\n");
72 dfii_pird_address_write(addr
);
73 dfii_pird_baddress_write(0);
74 command_prd(DFII_COMMAND_CAS
|DFII_COMMAND_CS
|DFII_COMMAND_RDDATA
);
78 printf("%02x", MMPTR(0xe0001038+4*i
));
80 printf("%02x", MMPTR(0xe000108c+4*i
));
84 void ddrwr(char *startaddr
)
91 printf("ddrrd <address>\n");
94 addr
= strtoul(startaddr
, &c
, 0);
96 printf("incorrect address\n");
101 MMPTR(0xe0001018+4*i
) = i
;
102 MMPTR(0xe000106c+4*i
) = 0xf0 + i
;
105 dfii_piwr_address_write(addr
);
106 dfii_piwr_baddress_write(0);
107 command_pwr(DFII_COMMAND_CAS
|DFII_COMMAND_WE
|DFII_COMMAND_CS
|DFII_COMMAND_WRDATA
);
110 #define TEST_SIZE (4*1024*1024)
112 int memtest_silent(void)
114 volatile unsigned int *array
= (unsigned int *)SDRAM_BASE
;
117 unsigned int error_cnt
;
120 for(i
=0;i
<TEST_SIZE
/4;i
++) {
121 prv
= 1664525*prv
+ 1013904223;
127 for(i
=0;i
<TEST_SIZE
/4;i
++) {
128 prv
= 1664525*prv
+ 1013904223;
139 e
= memtest_silent();
141 printf("Memtest failed: %d/%d words incorrect\n", e
, TEST_SIZE
/4);
144 printf("Memtest OK\n");
151 printf("Initializing DDR SDRAM...\n");
154 dfii_control_write(DFII_CONTROL_SEL
|DFII_CONTROL_CKE
);