10 static void cdelay(int i
)
13 __asm__
volatile("nop");
18 static void setaddr(int a
)
20 CSR_DFII_AH_P0
= (a
& 0xff00) >> 8;
21 CSR_DFII_AL_P0
= a
& 0x00ff;
22 CSR_DFII_AH_P1
= (a
& 0xff00) >> 8;
23 CSR_DFII_AL_P1
= a
& 0x00ff;
26 static void command_p0(int cmd
)
28 CSR_DFII_COMMAND_P0
= cmd
;
29 CSR_DFII_COMMAND_ISSUE_P0
= 1;
32 static void command_p1(int cmd
)
34 CSR_DFII_COMMAND_P1
= cmd
;
35 CSR_DFII_COMMAND_ISSUE_P1
= 1;
38 static void init_sequence(void)
45 CSR_DFII_CONTROL
= DFII_CONTROL_CKE
;
49 command_p0(DFII_COMMAND_RAS
|DFII_COMMAND_WE
|DFII_COMMAND_CS
);
51 /* Load Extended Mode Register */
54 command_p0(DFII_COMMAND_RAS
|DFII_COMMAND_CAS
|DFII_COMMAND_WE
|DFII_COMMAND_CS
);
57 /* Load Mode Register */
58 setaddr(0x0132); /* Reset DLL, CL=3, BL=4 */
59 command_p0(DFII_COMMAND_RAS
|DFII_COMMAND_CAS
|DFII_COMMAND_WE
|DFII_COMMAND_CS
);
64 command_p0(DFII_COMMAND_RAS
|DFII_COMMAND_WE
|DFII_COMMAND_CS
);
69 command_p0(DFII_COMMAND_RAS
|DFII_COMMAND_CAS
|DFII_COMMAND_CS
);
73 /* Load Mode Register */
74 setaddr(0x0032); /* CL=3, BL=4 */
75 command_p0(DFII_COMMAND_RAS
|DFII_COMMAND_CAS
|DFII_COMMAND_WE
|DFII_COMMAND_CS
);
81 CSR_DFII_CONTROL
= DFII_CONTROL_CKE
;
82 printf("DDR now under software control\n");
87 CSR_DFII_CONTROL
= DFII_CONTROL_SEL
|DFII_CONTROL_CKE
;
88 printf("DDR now under hardware control\n");
91 void ddrrow(char *_row
)
99 command_p0(DFII_COMMAND_RAS
|DFII_COMMAND_WE
|DFII_COMMAND_CS
);
101 printf("Precharged\n");
103 row
= strtoul(_row
, &c
, 0);
105 printf("incorrect row\n");
110 command_p0(DFII_COMMAND_RAS
|DFII_COMMAND_CS
);
112 printf("Activated row %d\n", row
);
116 void ddrrd(char *startaddr
)
122 if(*startaddr
== 0) {
123 printf("ddrrd <address>\n");
126 addr
= strtoul(startaddr
, &c
, 0);
128 printf("incorrect address\n");
134 command_p0(DFII_COMMAND_CAS
|DFII_COMMAND_CS
|DFII_COMMAND_RDDATA
);
138 printf("%02x", MMPTR(0xe0000834+4*i
));
140 printf("%02x", MMPTR(0xe0000884+4*i
));
144 void ddrwr(char *startaddr
)
150 if(*startaddr
== 0) {
151 printf("ddrrd <address>\n");
154 addr
= strtoul(startaddr
, &c
, 0);
156 printf("incorrect address\n");
161 MMPTR(0xe0000814+4*i
) = i
;
162 MMPTR(0xe0000864+4*i
) = 0xf0 + i
;
167 command_p1(DFII_COMMAND_CAS
|DFII_COMMAND_WE
|DFII_COMMAND_CS
|DFII_COMMAND_WRDATA
);
170 #define TEST_SIZE (4*1024*1024)
172 int memtest_silent(void)
174 volatile unsigned int *array
= (unsigned int *)SDRAM_BASE
;
179 for(i
=0;i
<TEST_SIZE
/4;i
++) {
180 prv
= 1664525*prv
+ 1013904223;
185 for(i
=0;i
<TEST_SIZE
/4;i
++) {
186 prv
= 1664525*prv
+ 1013904223;
203 printf("Initializing DDR SDRAM...\n");
206 CSR_DFII_CONTROL
= DFII_CONTROL_SEL
|DFII_CONTROL_CKE
;
207 if(!memtest_silent())
213 static const char *format_slot_state(int state
)
216 case 0: return "Empty";
217 case 1: return "Pending";
218 case 2: return "Processing";
219 default: return "UNEXPECTED VALUE";
225 volatile unsigned int *regs
= (unsigned int *)ASMIPROBE_BASE
;
232 slot_count
= regs
[offset
++];
233 trace_depth
= regs
[offset
++];
234 for(i
=0;i
<slot_count
;i
++)
235 printf("Slot #%d: %s\n", i
, format_slot_state(regs
[offset
++]));
236 printf("Latest tags:\n");
237 for(i
=0;i
<trace_depth
;i
++)
238 printf("%d ", regs
[offset
++]);