65b74bff25c84a953c76dd581a03c111112b2f8b
1 from nmigen
import Module
, Signal
2 from nmigen
.cli
import main
, verilog
4 from fpbase
import FPNum
, FPOp
, Overflow
, FPBase
9 def __init__(self
, width
):
13 self
.in_a
= FPOp(width
)
14 self
.in_b
= FPOp(width
)
15 self
.out_z
= FPOp(width
)
17 def get_fragment(self
, platform
=None):
18 """ creates the HDL code-fragment for FPMUL
23 a
= FPNum(self
.width
, False)
24 b
= FPNum(self
.width
, False)
25 z
= FPNum(self
.width
, False)
27 tot
= Signal(28) # sticky/round/guard bits, 23 result, 1 overflow
33 with m
.State("get_a"):
35 m
.d
.sync
+= s
.in_a
.ack
.eq(1)
36 with m
.If(s
.in_a
.ack
& in_a
.stb
):
42 with m
.State("get_b"):
44 m
.d
.sync
+= s
.in_b
.ack
.eq(1)
45 with m
.If(s
.in_b
.ack
& in_b
.stb
):
51 with m
.State("unpack"):
52 m
.next
+= "special_cases"
56 a
.e
.eq(a
[23:31] - 127),
57 b
.e
.eq(b
[23:31] - 127),
62 with m
.State("special_cases"):
63 m
.next
= "normalise_a"
64 #if a or b is NaN return NaN
65 with m
.If(a
.is_nan() | b
.is_nan()):
68 #if a is inf return inf
69 with m
.Elif(a
.is_inf()):
72 #if b is zero return NaN
73 with m
.If(b
.is_zero()):
75 #if b is inf return inf
76 with m
.Elif(b
.is_inf()):
79 #if a is zero return NaN
80 with m
.If(a
.is_zero()):
83 #if a is zero return zero
84 with m
.Elif(a
.is_zero()):
87 #if b is zero return zero
88 with m
.Elif(b
.is_zero()):
91 # Denormalised Number checks
93 m
.next
+= "normalise_a"
94 self
.denormalise(m
, a
)
95 self
.denormalise(m
, b
)
100 with m
.State("normalise_a"):
101 self
.op_normalise(m
, a
, "normalise_b")
106 with m
.State("normalise_b"):
107 self
.op_normalise(m
, b
, "multiply_0")
110 with m
.State("multiply_0"):
111 m
.next
+= "multiply_1"
114 z
.e
.eq(a
.e
+ b
.e
+ 1),
115 product
.eq(a
.m
* b
.m
* 4)
119 with m
.State("multiply_1"):
120 m
.next
+= "normalise_1"
122 z
.m
.eq(product
[26:50]),
123 guard
.eq(product
[25]),
124 round_bit
.eq(product
[24]),
125 sticky
.eq(product
[0:23] != 0)
129 # First stage of normalisation.
130 with m
.State("normalise_1"):
131 self
.normalise_1(m
, z
, of
, "normalise_2")
134 # Second stage of normalisation.
136 with m
.State("normalise_2"):
137 self
.normalise_2(m
, z
, of
, "round")
142 with m
.State("round"):
143 self
.roundz(m
, z
, of
, "corrections")
147 with m
.State("pack"):
148 self
.pack(m
, z
, "put_z")
153 with m
.State("put_z"):
154 self
.put_z(m
, z
, self
.out_z
, "get_a")
161 //if a is NaN or b is NaN return NaN
162 if ((a_e == 128 && a_m != 0) || (b_e == 128 && b_m != 0)) begin
168 //if a is inf return inf
169 end else if (a_e == 128) begin
173 //if b is zero return NaN
174 if (($signed(b_e) == -127) && (b_m == 0)) begin
181 //if b is inf return inf
182 end else if (b_e == 128) begin
186 //if a is zero return NaN
187 if (($signed(a_e) == -127) && (a_m == 0)) begin
194 //if a is zero return zero
195 end else if (($signed(a_e) == -127) && (a_m == 0)) begin
200 //if b is zero return zero
201 end else if (($signed(b_e) == -127) && (b_m == 0)) begin
208 //Denormalised Number
209 if ($signed(a_e) == -127) begin
214 //Denormalised Number
215 if ($signed(b_e) == -127) begin
220 state <= normalise_a;
227 state <= normalise_b;
247 z_e <= a_e + b_e + 1;
248 product <= a_m * b_m * 4;
254 z_m <= product[49:26];
255 guard <= product[25];
256 round_bit <= product[24];
257 sticky <= (product[23:0] != 0);
258 state <= normalise_1;
263 if (z_m[23] == 0) begin
270 state <= normalise_2;
276 if ($signed(z_e) < -126) begin
281 sticky <= sticky | round_bit;
289 if (guard && (round_bit | sticky | z_m[0])) begin
291 if (z_m == 24'hffffff) begin
300 z[22 : 0] <= z_m[22:0];
301 z[30 : 23] <= z_e[7:0] + 127;
303 if ($signed(z_e) == -126 && z_m[23] == 0) begin
308 if ($signed(z_e) > 127) begin
320 if (s_output_z_stb && output_z_ack) begin
328 if __name__
== "__main__":
329 alu
= FPMUL(width
=32)
330 main(alu
, ports
=alu
.in_a
.ports() + alu
.in_b
.ports() + alu
.out_z
.ports())