02a9ba15938c7bd428fbd19a4f133756cc00ba62
1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
5 from nmigen
import Module
, Signal
, Cat
, Mux
6 from nmigen
.lib
.coding
import PriorityEncoder
7 from nmigen
.cli
import main
, verilog
9 from fpbase
import FPNumIn
, FPNumOut
, FPOp
, Overflow
, FPBase
, FPNumBase
10 from fpbase
import MultiShiftRMerge
11 #from fpbase import FPNumShiftMultiRight
13 class FPState(FPBase
):
14 def __init__(self
, state_from
):
15 self
.state_from
= state_from
17 def set_inputs(self
, inputs
):
19 for k
,v
in inputs
.items():
22 def set_outputs(self
, outputs
):
23 self
.outputs
= outputs
24 for k
,v
in outputs
.items():
29 def __init__(self
, width
):
30 self
.in_op
= FPOp(width
)
31 self
.out_op
= FPNumIn(self
.in_op
, width
)
32 self
.out_decode
= Signal(reset_less
=True)
34 def elaborate(self
, platform
):
36 m
.d
.comb
+= self
.out_decode
.eq((self
.in_op
.ack
) & (self
.in_op
.stb
))
37 #m.submodules.get_op_in = self.in_op
38 m
.submodules
.get_op_out
= self
.out_op
39 with m
.If(self
.out_decode
):
41 self
.out_op
.decode(self
.in_op
.v
),
46 class FPGetOp(FPState
):
50 def __init__(self
, in_state
, out_state
, in_op
, width
):
51 FPState
.__init
__(self
, in_state
)
52 self
.out_state
= out_state
53 self
.mod
= FPGetOpMod(width
)
55 self
.out_op
= FPNumIn(in_op
, width
)
56 self
.out_decode
= Signal(reset_less
=True)
58 def setup(self
, m
, in_op
):
59 """ links module to inputs and outputs
61 setattr(m
.submodules
, self
.state_from
, self
.mod
)
62 m
.d
.comb
+= self
.mod
.in_op
.copy(in_op
)
63 m
.d
.comb
+= self
.out_op
.v
.eq(self
.mod
.out_op
.v
)
64 m
.d
.comb
+= self
.out_decode
.eq(self
.mod
.out_decode
)
67 with m
.If(self
.out_decode
):
68 m
.next
= self
.out_state
71 self
.out_op
.copy(self
.mod
.out_op
)
74 m
.d
.sync
+= self
.in_op
.ack
.eq(1)
77 class FPGetOpB(FPState
):
81 def __init__(self
, in_b
, width
):
82 FPState
.__init
__(self
, "get_b")
84 self
.b
= FPNumIn(self
.in_b
, width
)
87 self
.get_op(m
, self
.in_b
, self
.b
, "special_cases")
90 class FPAddSpecialCasesMod
:
91 """ special cases: NaNs, infs, zeros, denormalised
92 NOTE: some of these are unique to add. see "Special Operations"
93 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
96 def __init__(self
, width
):
97 self
.in_a
= FPNumBase(width
)
98 self
.in_b
= FPNumBase(width
)
99 self
.out_z
= FPNumOut(width
, False)
100 self
.out_do_z
= Signal(reset_less
=True)
102 def setup(self
, m
, in_a
, in_b
, out_z
, out_do_z
):
103 """ links module to inputs and outputs
105 m
.d
.comb
+= self
.in_a
.copy(in_a
)
106 m
.d
.comb
+= self
.in_b
.copy(in_b
)
107 #m.d.comb += out_z.v.eq(self.out_z.v)
108 m
.d
.comb
+= out_do_z
.eq(self
.out_do_z
)
110 def elaborate(self
, platform
):
113 m
.submodules
.sc_in_a
= self
.in_a
114 m
.submodules
.sc_in_b
= self
.in_b
115 m
.submodules
.sc_out_z
= self
.out_z
118 m
.d
.comb
+= s_nomatch
.eq(self
.in_a
.s
!= self
.in_b
.s
)
121 m
.d
.comb
+= m_match
.eq(self
.in_a
.m
== self
.in_b
.m
)
123 # if a is NaN or b is NaN return NaN
124 with m
.If(self
.in_a
.is_nan | self
.in_b
.is_nan
):
125 m
.d
.comb
+= self
.out_do_z
.eq(1)
126 m
.d
.comb
+= self
.out_z
.nan(0)
128 # XXX WEIRDNESS for FP16 non-canonical NaN handling
131 ## if a is zero and b is NaN return -b
132 #with m.If(a.is_zero & (a.s==0) & b.is_nan):
133 # m.d.comb += self.out_do_z.eq(1)
134 # m.d.comb += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
136 ## if b is zero and a is NaN return -a
137 #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
138 # m.d.comb += self.out_do_z.eq(1)
139 # m.d.comb += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
141 ## if a is -zero and b is NaN return -b
142 #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
143 # m.d.comb += self.out_do_z.eq(1)
144 # m.d.comb += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
146 ## if b is -zero and a is NaN return -a
147 #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
148 # m.d.comb += self.out_do_z.eq(1)
149 # m.d.comb += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
151 # if a is inf return inf (or NaN)
152 with m
.Elif(self
.in_a
.is_inf
):
153 m
.d
.comb
+= self
.out_do_z
.eq(1)
154 m
.d
.comb
+= self
.out_z
.inf(self
.in_a
.s
)
155 # if a is inf and signs don't match return NaN
156 with m
.If(self
.in_b
.exp_128
& s_nomatch
):
157 m
.d
.comb
+= self
.out_z
.nan(0)
159 # if b is inf return inf
160 with m
.Elif(self
.in_b
.is_inf
):
161 m
.d
.comb
+= self
.out_do_z
.eq(1)
162 m
.d
.comb
+= self
.out_z
.inf(self
.in_b
.s
)
164 # if a is zero and b zero return signed-a/b
165 with m
.Elif(self
.in_a
.is_zero
& self
.in_b
.is_zero
):
166 m
.d
.comb
+= self
.out_do_z
.eq(1)
167 m
.d
.comb
+= self
.out_z
.create(self
.in_a
.s
& self
.in_b
.s
,
171 # if a is zero return b
172 with m
.Elif(self
.in_a
.is_zero
):
173 m
.d
.comb
+= self
.out_do_z
.eq(1)
174 m
.d
.comb
+= self
.out_z
.create(self
.in_b
.s
, self
.in_b
.e
,
177 # if b is zero return a
178 with m
.Elif(self
.in_b
.is_zero
):
179 m
.d
.comb
+= self
.out_do_z
.eq(1)
180 m
.d
.comb
+= self
.out_z
.create(self
.in_a
.s
, self
.in_a
.e
,
183 # if a equal to -b return zero (+ve zero)
184 with m
.Elif(s_nomatch
& m_match
& (self
.in_a
.e
== self
.in_b
.e
)):
185 m
.d
.comb
+= self
.out_do_z
.eq(1)
186 m
.d
.comb
+= self
.out_z
.zero(0)
188 # Denormalised Number checks
190 m
.d
.comb
+= self
.out_do_z
.eq(0)
195 class FPAddSpecialCases(FPState
):
196 """ special cases: NaNs, infs, zeros, denormalised
197 NOTE: some of these are unique to add. see "Special Operations"
198 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
201 def __init__(self
, width
):
202 FPState
.__init
__(self
, "special_cases")
203 self
.mod
= FPAddSpecialCasesMod(width
)
204 self
.out_z
= FPNumOut(width
, False)
205 self
.out_do_z
= Signal(reset_less
=True)
208 with m
.If(self
.out_do_z
):
209 m
.d
.sync
+= self
.out_z
.v
.eq(self
.mod
.out_z
.v
) # only take the output
212 m
.next
= "denormalise"
215 class FPAddDeNormMod(FPState
):
217 def __init__(self
, width
):
218 self
.in_a
= FPNumBase(width
)
219 self
.in_b
= FPNumBase(width
)
220 self
.out_a
= FPNumBase(width
)
221 self
.out_b
= FPNumBase(width
)
223 def elaborate(self
, platform
):
225 m
.submodules
.denorm_in_a
= self
.in_a
226 m
.submodules
.denorm_in_b
= self
.in_b
227 m
.submodules
.denorm_out_a
= self
.out_a
228 m
.submodules
.denorm_out_b
= self
.out_b
229 # hmmm, don't like repeating identical code
230 m
.d
.comb
+= self
.out_a
.copy(self
.in_a
)
231 with m
.If(self
.in_a
.exp_n127
):
232 m
.d
.comb
+= self
.out_a
.e
.eq(self
.in_a
.N126
) # limit a exponent
234 m
.d
.comb
+= self
.out_a
.m
[-1].eq(1) # set top mantissa bit
236 m
.d
.comb
+= self
.out_b
.copy(self
.in_b
)
237 with m
.If(self
.in_b
.exp_n127
):
238 m
.d
.comb
+= self
.out_b
.e
.eq(self
.in_b
.N126
) # limit a exponent
240 m
.d
.comb
+= self
.out_b
.m
[-1].eq(1) # set top mantissa bit
245 class FPAddDeNorm(FPState
):
247 def __init__(self
, width
):
248 FPState
.__init
__(self
, "denormalise")
249 self
.mod
= FPAddDeNormMod(width
)
250 self
.out_a
= FPNumBase(width
)
251 self
.out_b
= FPNumBase(width
)
253 def setup(self
, m
, in_a
, in_b
):
254 """ links module to inputs and outputs
256 m
.submodules
.denormalise
= self
.mod
257 m
.d
.comb
+= self
.mod
.in_a
.copy(in_a
)
258 m
.d
.comb
+= self
.mod
.in_b
.copy(in_b
)
261 # Denormalised Number checks
263 m
.d
.sync
+= self
.out_a
.copy(self
.mod
.out_a
)
264 m
.d
.sync
+= self
.out_b
.copy(self
.mod
.out_b
)
267 class FPAddAlignMultiMod(FPState
):
269 def __init__(self
, width
):
270 self
.in_a
= FPNumBase(width
)
271 self
.in_b
= FPNumBase(width
)
272 self
.out_a
= FPNumIn(None, width
)
273 self
.out_b
= FPNumIn(None, width
)
274 self
.exp_eq
= Signal(reset_less
=True)
276 def elaborate(self
, platform
):
277 # This one however (single-cycle) will do the shift
282 m
.submodules
.align_in_a
= self
.in_a
283 m
.submodules
.align_in_b
= self
.in_b
284 m
.submodules
.align_out_a
= self
.out_a
285 m
.submodules
.align_out_b
= self
.out_b
287 # NOTE: this does *not* do single-cycle multi-shifting,
288 # it *STAYS* in the align state until exponents match
290 # exponent of a greater than b: shift b down
291 m
.d
.comb
+= self
.exp_eq
.eq(0)
292 m
.d
.comb
+= self
.out_a
.copy(self
.in_a
)
293 m
.d
.comb
+= self
.out_b
.copy(self
.in_b
)
294 agtb
= Signal(reset_less
=True)
295 altb
= Signal(reset_less
=True)
296 m
.d
.comb
+= agtb
.eq(self
.in_a
.e
> self
.in_b
.e
)
297 m
.d
.comb
+= altb
.eq(self
.in_a
.e
< self
.in_b
.e
)
299 m
.d
.comb
+= self
.out_b
.shift_down(self
.in_b
)
300 # exponent of b greater than a: shift a down
302 m
.d
.comb
+= self
.out_a
.shift_down(self
.in_a
)
303 # exponents equal: move to next stage.
305 m
.d
.comb
+= self
.exp_eq
.eq(1)
309 class FPAddAlignMulti(FPState
):
311 def __init__(self
, width
):
312 FPState
.__init
__(self
, "align")
313 self
.mod
= FPAddAlignMultiMod(width
)
314 self
.out_a
= FPNumIn(None, width
)
315 self
.out_b
= FPNumIn(None, width
)
316 self
.exp_eq
= Signal(reset_less
=True)
318 def setup(self
, m
, in_a
, in_b
):
319 """ links module to inputs and outputs
321 m
.submodules
.align
= self
.mod
322 m
.d
.comb
+= self
.mod
.in_a
.copy(in_a
)
323 m
.d
.comb
+= self
.mod
.in_b
.copy(in_b
)
324 #m.d.comb += self.out_a.copy(self.mod.out_a)
325 #m.d.comb += self.out_b.copy(self.mod.out_b)
326 m
.d
.comb
+= self
.exp_eq
.eq(self
.mod
.exp_eq
)
329 m
.d
.sync
+= self
.out_a
.copy(self
.mod
.out_a
)
330 m
.d
.sync
+= self
.out_b
.copy(self
.mod
.out_b
)
331 with m
.If(self
.exp_eq
):
335 class FPAddAlignSingleMod
:
337 def __init__(self
, width
):
339 self
.in_a
= FPNumBase(width
)
340 self
.in_b
= FPNumBase(width
)
341 self
.out_a
= FPNumIn(None, width
)
342 self
.out_b
= FPNumIn(None, width
)
344 def elaborate(self
, platform
):
345 """ Aligns A against B or B against A, depending on which has the
346 greater exponent. This is done in a *single* cycle using
347 variable-width bit-shift
349 the shifter used here is quite expensive in terms of gates.
350 Mux A or B in (and out) into temporaries, as only one of them
351 needs to be aligned against the other
355 m
.submodules
.align_in_a
= self
.in_a
356 m
.submodules
.align_in_b
= self
.in_b
357 m
.submodules
.align_out_a
= self
.out_a
358 m
.submodules
.align_out_b
= self
.out_b
360 # temporary (muxed) input and output to be shifted
361 t_inp
= FPNumBase(self
.width
)
362 t_out
= FPNumIn(None, self
.width
)
363 espec
= (len(self
.in_a
.e
), True)
364 msr
= MultiShiftRMerge(self
.in_a
.m_width
, espec
)
365 m
.submodules
.align_t_in
= t_inp
366 m
.submodules
.align_t_out
= t_out
367 m
.submodules
.multishift_r
= msr
369 ediff
= Signal(espec
, reset_less
=True)
370 ediffr
= Signal(espec
, reset_less
=True)
371 tdiff
= Signal(espec
, reset_less
=True)
372 elz
= Signal(reset_less
=True)
373 egz
= Signal(reset_less
=True)
375 # connect multi-shifter to t_inp/out mantissa (and tdiff)
376 m
.d
.comb
+= msr
.inp
.eq(t_inp
.m
)
377 m
.d
.comb
+= msr
.diff
.eq(tdiff
)
378 m
.d
.comb
+= t_out
.m
.eq(msr
.m
)
379 m
.d
.comb
+= t_out
.e
.eq(t_inp
.e
+ tdiff
)
380 m
.d
.comb
+= t_out
.s
.eq(t_inp
.s
)
382 m
.d
.comb
+= ediff
.eq(self
.in_a
.e
- self
.in_b
.e
)
383 m
.d
.comb
+= ediffr
.eq(self
.in_b
.e
- self
.in_a
.e
)
384 m
.d
.comb
+= elz
.eq(self
.in_a
.e
< self
.in_b
.e
)
385 m
.d
.comb
+= egz
.eq(self
.in_a
.e
> self
.in_b
.e
)
387 # default: A-exp == B-exp, A and B untouched (fall through)
388 m
.d
.comb
+= self
.out_a
.copy(self
.in_a
)
389 m
.d
.comb
+= self
.out_b
.copy(self
.in_b
)
390 # only one shifter (muxed)
391 #m.d.comb += t_out.shift_down_multi(tdiff, t_inp)
392 # exponent of a greater than b: shift b down
394 m
.d
.comb
+= [t_inp
.copy(self
.in_b
),
396 self
.out_b
.copy(t_out
),
397 self
.out_b
.s
.eq(self
.in_b
.s
), # whoops forgot sign
399 # exponent of b greater than a: shift a down
401 m
.d
.comb
+= [t_inp
.copy(self
.in_a
),
403 self
.out_a
.copy(t_out
),
404 self
.out_a
.s
.eq(self
.in_a
.s
), # whoops forgot sign
409 class FPAddAlignSingle(FPState
):
411 def __init__(self
, width
):
412 FPState
.__init
__(self
, "align")
413 self
.mod
= FPAddAlignSingleMod(width
)
414 self
.out_a
= FPNumIn(None, width
)
415 self
.out_b
= FPNumIn(None, width
)
417 def setup(self
, m
, in_a
, in_b
):
418 """ links module to inputs and outputs
420 m
.submodules
.align
= self
.mod
421 m
.d
.comb
+= self
.mod
.in_a
.copy(in_a
)
422 m
.d
.comb
+= self
.mod
.in_b
.copy(in_b
)
425 # NOTE: could be done as comb
426 m
.d
.sync
+= self
.out_a
.copy(self
.mod
.out_a
)
427 m
.d
.sync
+= self
.out_b
.copy(self
.mod
.out_b
)
431 class FPAddStage0Mod
:
433 def __init__(self
, width
):
434 self
.in_a
= FPNumBase(width
)
435 self
.in_b
= FPNumBase(width
)
436 self
.in_z
= FPNumBase(width
, False)
437 self
.out_z
= FPNumBase(width
, False)
438 self
.out_tot
= Signal(self
.out_z
.m_width
+ 4, reset_less
=True)
440 def elaborate(self
, platform
):
442 m
.submodules
.add0_in_a
= self
.in_a
443 m
.submodules
.add0_in_b
= self
.in_b
444 m
.submodules
.add0_out_z
= self
.out_z
446 m
.d
.comb
+= self
.out_z
.e
.eq(self
.in_a
.e
)
448 # store intermediate tests (and zero-extended mantissas)
449 seq
= Signal(reset_less
=True)
450 mge
= Signal(reset_less
=True)
451 am0
= Signal(len(self
.in_a
.m
)+1, reset_less
=True)
452 bm0
= Signal(len(self
.in_b
.m
)+1, reset_less
=True)
453 m
.d
.comb
+= [seq
.eq(self
.in_a
.s
== self
.in_b
.s
),
454 mge
.eq(self
.in_a
.m
>= self
.in_b
.m
),
455 am0
.eq(Cat(self
.in_a
.m
, 0)),
456 bm0
.eq(Cat(self
.in_b
.m
, 0))
458 # same-sign (both negative or both positive) add mantissas
461 self
.out_tot
.eq(am0
+ bm0
),
462 self
.out_z
.s
.eq(self
.in_a
.s
)
464 # a mantissa greater than b, use a
467 self
.out_tot
.eq(am0
- bm0
),
468 self
.out_z
.s
.eq(self
.in_a
.s
)
470 # b mantissa greater than a, use b
473 self
.out_tot
.eq(bm0
- am0
),
474 self
.out_z
.s
.eq(self
.in_b
.s
)
479 class FPAddStage0(FPState
):
480 """ First stage of add. covers same-sign (add) and subtract
481 special-casing when mantissas are greater or equal, to
482 give greatest accuracy.
485 def __init__(self
, width
):
486 FPState
.__init
__(self
, "add_0")
487 self
.mod
= FPAddStage0Mod(width
)
488 self
.out_z
= FPNumBase(width
, False)
489 self
.out_tot
= Signal(self
.out_z
.m_width
+ 4, reset_less
=True)
491 def setup(self
, m
, in_a
, in_b
):
492 """ links module to inputs and outputs
494 m
.submodules
.add0
= self
.mod
496 m
.d
.comb
+= self
.mod
.in_a
.copy(in_a
)
497 m
.d
.comb
+= self
.mod
.in_b
.copy(in_b
)
501 # NOTE: these could be done as combinatorial (merge add0+add1)
502 m
.d
.sync
+= self
.out_z
.copy(self
.mod
.out_z
)
503 m
.d
.sync
+= self
.out_tot
.eq(self
.mod
.out_tot
)
506 class FPAddStage1Mod(FPState
):
507 """ Second stage of add: preparation for normalisation.
508 detects when tot sum is too big (tot[27] is kinda a carry bit)
511 def __init__(self
, width
):
512 self
.out_norm
= Signal(reset_less
=True)
513 self
.in_z
= FPNumBase(width
, False)
514 self
.in_tot
= Signal(self
.in_z
.m_width
+ 4, reset_less
=True)
515 self
.out_z
= FPNumBase(width
, False)
516 self
.out_of
= Overflow()
518 def elaborate(self
, platform
):
520 #m.submodules.norm1_in_overflow = self.in_of
521 #m.submodules.norm1_out_overflow = self.out_of
522 #m.submodules.norm1_in_z = self.in_z
523 #m.submodules.norm1_out_z = self.out_z
524 m
.d
.comb
+= self
.out_z
.copy(self
.in_z
)
525 # tot[27] gets set when the sum overflows. shift result down
526 with m
.If(self
.in_tot
[-1]):
528 self
.out_z
.m
.eq(self
.in_tot
[4:]),
529 self
.out_of
.m0
.eq(self
.in_tot
[4]),
530 self
.out_of
.guard
.eq(self
.in_tot
[3]),
531 self
.out_of
.round_bit
.eq(self
.in_tot
[2]),
532 self
.out_of
.sticky
.eq(self
.in_tot
[1] | self
.in_tot
[0]),
533 self
.out_z
.e
.eq(self
.in_z
.e
+ 1)
538 self
.out_z
.m
.eq(self
.in_tot
[3:]),
539 self
.out_of
.m0
.eq(self
.in_tot
[3]),
540 self
.out_of
.guard
.eq(self
.in_tot
[2]),
541 self
.out_of
.round_bit
.eq(self
.in_tot
[1]),
542 self
.out_of
.sticky
.eq(self
.in_tot
[0])
547 class FPAddStage1(FPState
):
549 def __init__(self
, width
):
550 FPState
.__init
__(self
, "add_1")
551 self
.mod
= FPAddStage1Mod(width
)
552 self
.out_z
= FPNumBase(width
, False)
553 self
.out_of
= Overflow()
554 self
.norm_stb
= Signal()
556 def setup(self
, m
, in_tot
, in_z
):
557 """ links module to inputs and outputs
559 m
.submodules
.add1
= self
.mod
561 m
.d
.comb
+= self
.mod
.in_z
.copy(in_z
)
562 m
.d
.comb
+= self
.mod
.in_tot
.eq(in_tot
)
564 m
.d
.sync
+= self
.norm_stb
.eq(0) # sets to zero when not in add1 state
567 m
.submodules
.add1_out_overflow
= self
.out_of
568 m
.d
.sync
+= self
.out_of
.copy(self
.mod
.out_of
)
569 m
.d
.sync
+= self
.out_z
.copy(self
.mod
.out_z
)
570 m
.d
.sync
+= self
.norm_stb
.eq(1)
571 m
.next
= "normalise_1"
574 class FPNorm1ModSingle
:
576 def __init__(self
, width
):
578 self
.in_select
= Signal(reset_less
=True)
579 self
.out_norm
= Signal(reset_less
=True)
580 self
.in_z
= FPNumBase(width
, False)
581 self
.in_of
= Overflow()
582 self
.temp_z
= FPNumBase(width
, False)
583 self
.temp_of
= Overflow()
584 self
.out_z
= FPNumBase(width
, False)
585 self
.out_of
= Overflow()
587 def elaborate(self
, platform
):
590 mwid
= self
.out_z
.m_width
+2
591 pe
= PriorityEncoder(mwid
)
592 m
.submodules
.norm_pe
= pe
594 m
.submodules
.norm1_out_z
= self
.out_z
595 m
.submodules
.norm1_out_overflow
= self
.out_of
596 m
.submodules
.norm1_temp_z
= self
.temp_z
597 m
.submodules
.norm1_temp_of
= self
.temp_of
598 m
.submodules
.norm1_in_z
= self
.in_z
599 m
.submodules
.norm1_in_overflow
= self
.in_of
601 in_z
= FPNumBase(self
.width
, False)
603 m
.submodules
.norm1_insel_z
= in_z
604 m
.submodules
.norm1_insel_overflow
= in_of
606 espec
= (len(in_z
.e
), True)
607 ediff_n126
= Signal(espec
, reset_less
=True)
608 msr
= MultiShiftRMerge(mwid
, espec
)
609 m
.submodules
.multishift_r
= msr
611 # select which of temp or in z/of to use
612 with m
.If(self
.in_select
):
613 m
.d
.comb
+= in_z
.copy(self
.in_z
)
614 m
.d
.comb
+= in_of
.copy(self
.in_of
)
616 m
.d
.comb
+= in_z
.copy(self
.temp_z
)
617 m
.d
.comb
+= in_of
.copy(self
.temp_of
)
618 # initialise out from in (overridden below)
619 m
.d
.comb
+= self
.out_z
.copy(in_z
)
620 m
.d
.comb
+= self
.out_of
.copy(in_of
)
621 # normalisation increase/decrease conditions
622 decrease
= Signal(reset_less
=True)
623 increase
= Signal(reset_less
=True)
624 m
.d
.comb
+= decrease
.eq(in_z
.m_msbzero
& in_z
.exp_gt_n126
)
625 m
.d
.comb
+= increase
.eq(in_z
.exp_lt_n126
)
626 m
.d
.comb
+= self
.out_norm
.eq(0) # loop-end condition
629 # *sigh* not entirely obvious: count leading zeros (clz)
630 # with a PriorityEncoder: to find from the MSB
631 # we reverse the order of the bits.
632 temp_m
= Signal(mwid
, reset_less
=True)
633 temp_s
= Signal(mwid
+1, reset_less
=True)
634 clz
= Signal((len(in_z
.e
), True), reset_less
=True)
635 # make sure that the amount to decrease by does NOT
636 # go below the minimum non-INF/NaN exponent
637 limclz
= Mux(in_z
.exp_sub_n126
> pe
.o
, pe
.o
,
640 # cat round and guard bits back into the mantissa
641 temp_m
.eq(Cat(in_of
.round_bit
, in_of
.guard
, in_z
.m
)),
642 pe
.i
.eq(temp_m
[::-1]), # inverted
643 clz
.eq(limclz
), # count zeros from MSB down
644 temp_s
.eq(temp_m
<< clz
), # shift mantissa UP
645 self
.out_z
.e
.eq(in_z
.e
- clz
), # DECREASE exponent
646 self
.out_z
.m
.eq(temp_s
[2:]), # exclude bits 0&1
647 self
.out_of
.m0
.eq(temp_s
[2]), # copy of mantissa[0]
648 # overflow in bits 0..1: got shifted too (leave sticky)
649 self
.out_of
.guard
.eq(temp_s
[1]), # guard
650 self
.out_of
.round_bit
.eq(temp_s
[0]), # round
653 with m
.Elif(increase
):
654 temp_m
= Signal(mwid
+1, reset_less
=True)
656 temp_m
.eq(Cat(in_of
.sticky
, in_of
.round_bit
, in_of
.guard
,
658 ediff_n126
.eq(in_z
.N126
- in_z
.e
),
659 # connect multi-shifter to inp/out mantissa (and ediff)
661 msr
.diff
.eq(ediff_n126
),
662 self
.out_z
.m
.eq(msr
.m
[3:]),
663 self
.out_of
.m0
.eq(temp_s
[3]), # copy of mantissa[0]
664 # overflow in bits 0..1: got shifted too (leave sticky)
665 self
.out_of
.guard
.eq(temp_s
[2]), # guard
666 self
.out_of
.round_bit
.eq(temp_s
[1]), # round
667 self
.out_of
.sticky
.eq(temp_s
[0]), # sticky
668 self
.out_z
.e
.eq(in_z
.e
+ ediff_n126
),
674 class FPNorm1ModMulti
:
676 def __init__(self
, width
, single_cycle
=True):
678 self
.in_select
= Signal(reset_less
=True)
679 self
.out_norm
= Signal(reset_less
=True)
680 self
.in_z
= FPNumBase(width
, False)
681 self
.in_of
= Overflow()
682 self
.temp_z
= FPNumBase(width
, False)
683 self
.temp_of
= Overflow()
684 self
.out_z
= FPNumBase(width
, False)
685 self
.out_of
= Overflow()
687 def elaborate(self
, platform
):
690 m
.submodules
.norm1_out_z
= self
.out_z
691 m
.submodules
.norm1_out_overflow
= self
.out_of
692 m
.submodules
.norm1_temp_z
= self
.temp_z
693 m
.submodules
.norm1_temp_of
= self
.temp_of
694 m
.submodules
.norm1_in_z
= self
.in_z
695 m
.submodules
.norm1_in_overflow
= self
.in_of
697 in_z
= FPNumBase(self
.width
, False)
699 m
.submodules
.norm1_insel_z
= in_z
700 m
.submodules
.norm1_insel_overflow
= in_of
702 # select which of temp or in z/of to use
703 with m
.If(self
.in_select
):
704 m
.d
.comb
+= in_z
.copy(self
.in_z
)
705 m
.d
.comb
+= in_of
.copy(self
.in_of
)
707 m
.d
.comb
+= in_z
.copy(self
.temp_z
)
708 m
.d
.comb
+= in_of
.copy(self
.temp_of
)
709 # initialise out from in (overridden below)
710 m
.d
.comb
+= self
.out_z
.copy(in_z
)
711 m
.d
.comb
+= self
.out_of
.copy(in_of
)
712 # normalisation increase/decrease conditions
713 decrease
= Signal(reset_less
=True)
714 increase
= Signal(reset_less
=True)
715 m
.d
.comb
+= decrease
.eq(in_z
.m_msbzero
& in_z
.exp_gt_n126
)
716 m
.d
.comb
+= increase
.eq(in_z
.exp_lt_n126
)
717 m
.d
.comb
+= self
.out_norm
.eq(decrease | increase
) # loop-end
721 self
.out_z
.e
.eq(in_z
.e
- 1), # DECREASE exponent
722 self
.out_z
.m
.eq(in_z
.m
<< 1), # shift mantissa UP
723 self
.out_z
.m
[0].eq(in_of
.guard
), # steal guard (was tot[2])
724 self
.out_of
.guard
.eq(in_of
.round_bit
), # round (was tot[1])
725 self
.out_of
.round_bit
.eq(0), # reset round bit
726 self
.out_of
.m0
.eq(in_of
.guard
),
729 with m
.Elif(increase
):
731 self
.out_z
.e
.eq(in_z
.e
+ 1), # INCREASE exponent
732 self
.out_z
.m
.eq(in_z
.m
>> 1), # shift mantissa DOWN
733 self
.out_of
.guard
.eq(in_z
.m
[0]),
734 self
.out_of
.m0
.eq(in_z
.m
[1]),
735 self
.out_of
.round_bit
.eq(in_of
.guard
),
736 self
.out_of
.sticky
.eq(in_of
.sticky | in_of
.round_bit
)
742 class FPNorm1(FPState
):
744 def __init__(self
, width
, single_cycle
=True):
745 FPState
.__init
__(self
, "normalise_1")
747 self
.mod
= FPNorm1ModSingle(width
)
749 self
.mod
= FPNorm1ModMulti(width
)
750 self
.stb
= Signal(reset_less
=True)
751 self
.ack
= Signal(reset
=0, reset_less
=True)
752 self
.out_norm
= Signal(reset_less
=True)
753 self
.in_accept
= Signal(reset_less
=True)
754 self
.temp_z
= FPNumBase(width
)
755 self
.temp_of
= Overflow()
756 self
.out_z
= FPNumBase(width
)
757 self
.out_roundz
= Signal(reset_less
=True)
759 def setup(self
, m
, in_z
, in_of
, norm_stb
):
760 """ links module to inputs and outputs
762 m
.submodules
.normalise_1
= self
.mod
764 m
.d
.comb
+= self
.mod
.in_z
.copy(in_z
)
765 m
.d
.comb
+= self
.mod
.in_of
.copy(in_of
)
767 m
.d
.comb
+= self
.mod
.in_select
.eq(self
.in_accept
)
768 m
.d
.comb
+= self
.mod
.temp_z
.copy(self
.temp_z
)
769 m
.d
.comb
+= self
.mod
.temp_of
.copy(self
.temp_of
)
771 m
.d
.comb
+= self
.out_z
.copy(self
.mod
.out_z
)
772 m
.d
.comb
+= self
.out_norm
.eq(self
.mod
.out_norm
)
774 m
.d
.comb
+= self
.stb
.eq(norm_stb
)
775 m
.d
.sync
+= self
.ack
.eq(0) # sets to zero when not in normalise_1 state
779 m
.d
.comb
+= self
.in_accept
.eq((~self
.ack
) & (self
.stb
))
780 m
.d
.sync
+= self
.temp_of
.copy(self
.mod
.out_of
)
781 m
.d
.sync
+= self
.temp_z
.copy(self
.out_z
)
782 with m
.If(self
.out_norm
):
783 with m
.If(self
.in_accept
):
788 m
.d
.sync
+= self
.ack
.eq(0)
790 # normalisation not required (or done).
792 m
.d
.sync
+= self
.ack
.eq(1)
793 m
.d
.sync
+= self
.out_roundz
.eq(self
.mod
.out_of
.roundz
)
798 def __init__(self
, width
):
799 self
.in_roundz
= Signal(reset_less
=True)
800 self
.in_z
= FPNumBase(width
, False)
801 self
.out_z
= FPNumBase(width
, False)
803 def elaborate(self
, platform
):
805 m
.d
.comb
+= self
.out_z
.copy(self
.in_z
)
806 with m
.If(self
.in_roundz
):
807 m
.d
.comb
+= self
.out_z
.m
.eq(self
.in_z
.m
+ 1) # mantissa rounds up
808 with m
.If(self
.in_z
.m
== self
.in_z
.m1s
): # all 1s
809 m
.d
.comb
+= self
.out_z
.e
.eq(self
.in_z
.e
+ 1) # exponent up
813 class FPRound(FPState
):
815 def __init__(self
, width
):
816 FPState
.__init
__(self
, "round")
817 self
.mod
= FPRoundMod(width
)
818 self
.out_z
= FPNumBase(width
)
820 def setup(self
, m
, in_z
, roundz
):
821 """ links module to inputs and outputs
823 m
.submodules
.roundz
= self
.mod
825 m
.d
.comb
+= self
.mod
.in_z
.copy(in_z
)
826 m
.d
.comb
+= self
.mod
.in_roundz
.eq(roundz
)
829 m
.d
.sync
+= self
.out_z
.copy(self
.mod
.out_z
)
830 m
.next
= "corrections"
833 class FPCorrectionsMod
:
835 def __init__(self
, width
):
836 self
.in_z
= FPNumOut(width
, False)
837 self
.out_z
= FPNumOut(width
, False)
839 def elaborate(self
, platform
):
841 m
.submodules
.corr_in_z
= self
.in_z
842 m
.submodules
.corr_out_z
= self
.out_z
843 m
.d
.comb
+= self
.out_z
.copy(self
.in_z
)
844 with m
.If(self
.in_z
.is_denormalised
):
845 m
.d
.comb
+= self
.out_z
.e
.eq(self
.in_z
.N127
)
847 # with m.If(self.in_z.is_overflowed):
848 # m.d.comb += self.out_z.inf(self.in_z.s)
850 # m.d.comb += self.out_z.create(self.in_z.s, self.in_z.e, self.in_z.m)
854 class FPCorrections(FPState
):
856 def __init__(self
, width
):
857 FPState
.__init
__(self
, "corrections")
858 self
.mod
= FPCorrectionsMod(width
)
859 self
.out_z
= FPNumBase(width
)
861 def setup(self
, m
, in_z
):
862 """ links module to inputs and outputs
864 m
.submodules
.corrections
= self
.mod
865 m
.d
.comb
+= self
.mod
.in_z
.copy(in_z
)
868 m
.d
.sync
+= self
.out_z
.copy(self
.mod
.out_z
)
874 def __init__(self
, width
):
875 self
.in_z
= FPNumOut(width
, False)
876 self
.out_z
= FPNumOut(width
, False)
878 def elaborate(self
, platform
):
880 m
.submodules
.pack_in_z
= self
.in_z
881 with m
.If(self
.in_z
.is_overflowed
):
882 m
.d
.comb
+= self
.out_z
.inf(self
.in_z
.s
)
884 m
.d
.comb
+= self
.out_z
.create(self
.in_z
.s
, self
.in_z
.e
, self
.in_z
.m
)
888 class FPPack(FPState
):
890 def __init__(self
, width
):
891 FPState
.__init
__(self
, "pack")
892 self
.mod
= FPPackMod(width
)
893 self
.out_z
= FPNumOut(width
, False)
895 def setup(self
, m
, in_z
):
896 """ links module to inputs and outputs
898 m
.submodules
.pack
= self
.mod
899 m
.d
.comb
+= self
.mod
.in_z
.copy(in_z
)
902 m
.d
.sync
+= self
.out_z
.v
.eq(self
.mod
.out_z
.v
)
903 m
.next
= "pack_put_z"
906 class FPPutZ(FPState
):
908 def __init__(self
, state
, in_z
, out_z
):
909 FPState
.__init
__(self
, state
)
915 self
.out_z
.v
.eq(self
.in_z
.v
)
917 with m
.If(self
.out_z
.stb
& self
.out_z
.ack
):
918 m
.d
.sync
+= self
.out_z
.stb
.eq(0)
921 m
.d
.sync
+= self
.out_z
.stb
.eq(1)
926 def __init__(self
, width
, single_cycle
=False):
928 self
.single_cycle
= single_cycle
930 self
.in_a
= FPOp(width
)
931 self
.in_b
= FPOp(width
)
932 self
.out_z
= FPOp(width
)
936 def add_state(self
, state
):
937 self
.states
.append(state
)
940 def get_fragment(self
, platform
=None):
941 """ creates the HDL code-fragment for FPAdd
944 m
.submodules
.in_a
= self
.in_a
945 m
.submodules
.in_b
= self
.in_b
946 m
.submodules
.out_z
= self
.out_z
948 geta
= self
.add_state(FPGetOp("get_a", "get_b",
949 self
.in_a
, self
.width
))
950 geta
.setup(m
, self
.in_a
)
953 getb
= self
.add_state(FPGetOp("get_b", "special_cases",
954 self
.in_b
, self
.width
))
955 getb
.setup(m
, self
.in_b
)
958 sc
= self
.add_state(FPAddSpecialCases(self
.width
))
959 sc
.mod
.setup(m
, a
, b
, sc
.out_z
, sc
.out_do_z
)
960 m
.submodules
.specialcases
= sc
.mod
962 dn
= self
.add_state(FPAddDeNorm(self
.width
))
965 if self
.single_cycle
:
966 alm
= self
.add_state(FPAddAlignSingle(self
.width
))
967 alm
.setup(m
, dn
.out_a
, dn
.out_b
)
969 alm
= self
.add_state(FPAddAlignMulti(self
.width
))
970 #alm.set_inputs({"a": a, "b": b})
971 alm
.setup(m
, dn
.out_a
, dn
.out_b
)
973 add0
= self
.add_state(FPAddStage0(self
.width
))
974 add0
.setup(m
, alm
.out_a
, alm
.out_b
)
976 add1
= self
.add_state(FPAddStage1(self
.width
))
977 add1
.setup(m
, add0
.out_tot
, add0
.out_z
)
979 n1
= self
.add_state(FPNorm1(self
.width
))
980 n1
.setup(m
, add1
.out_z
, add1
.out_of
, add1
.norm_stb
)
982 rn
= self
.add_state(FPRound(self
.width
))
983 rn
.setup(m
, n1
.out_z
, n1
.out_roundz
)
985 cor
= self
.add_state(FPCorrections(self
.width
))
986 cor
.setup(m
, rn
.out_z
)
988 pa
= self
.add_state(FPPack(self
.width
))
989 pa
.setup(m
, cor
.out_z
)
991 ppz
= self
.add_state(FPPutZ("pack_put_z", pa
.out_z
, self
.out_z
))
993 pz
= self
.add_state(FPPutZ("put_z", sc
.out_z
, self
.out_z
))
997 for state
in self
.states
:
998 with m
.State(state
.state_from
):
1004 if __name__
== "__main__":
1005 alu
= FPADD(width
=32, single_cycle
=True)
1006 main(alu
, ports
=alu
.in_a
.ports() + alu
.in_b
.ports() + alu
.out_z
.ports())
1009 # works... but don't use, just do "python fname.py convert -t v"
1010 #print (verilog.convert(alu, ports=[
1011 # ports=alu.in_a.ports() + \
1012 # alu.in_b.ports() + \
1013 # alu.out_z.ports())