15745cfa1088733df441977e133ece774454ba91
1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
5 from nmigen
import Module
, Signal
, Cat
, Mux
, Array
, Const
6 from nmigen
.lib
.coding
import PriorityEncoder
7 from nmigen
.cli
import main
, verilog
10 from fpbase
import FPNumIn
, FPNumOut
, FPOp
, Overflow
, FPBase
, FPNumBase
11 from fpbase
import MultiShiftRMerge
, Trigger
12 #from fpbase import FPNumShiftMultiRight
15 class FPState(FPBase
):
16 def __init__(self
, state_from
):
17 self
.state_from
= state_from
19 def set_inputs(self
, inputs
):
21 for k
,v
in inputs
.items():
24 def set_outputs(self
, outputs
):
25 self
.outputs
= outputs
26 for k
,v
in outputs
.items():
30 class FPGetSyncOpsMod
:
31 def __init__(self
, width
, num_ops
=2):
33 self
.num_ops
= num_ops
36 for i
in range(num_ops
):
37 inops
.append(Signal(width
, reset_less
=True))
38 outops
.append(Signal(width
, reset_less
=True))
41 self
.stb
= Signal(num_ops
)
43 self
.ready
= Signal(reset_less
=True)
44 self
.out_decode
= Signal(reset_less
=True)
46 def elaborate(self
, platform
):
48 m
.d
.comb
+= self
.ready
.eq(self
.stb
== Const(-1, (self
.num_ops
, False)))
49 m
.d
.comb
+= self
.out_decode
.eq(self
.ack
& self
.ready
)
50 with m
.If(self
.out_decode
):
51 for i
in range(self
.num_ops
):
53 self
.out_op
[i
].eq(self
.in_op
[i
]),
58 return self
.in_op
+ self
.out_op
+ [self
.stb
, self
.ack
]
62 def __init__(self
, width
, num_ops
):
63 Trigger
.__init
__(self
)
65 self
.num_ops
= num_ops
68 for i
in range(num_ops
):
69 res
.append(Signal(width
))
74 for i
in range(self
.num_ops
):
82 def __init__(self
, width
, num_ops
=2, num_rows
=4):
84 self
.num_ops
= num_ops
85 self
.num_rows
= num_rows
86 self
.mmax
= int(log(self
.num_rows
) / log(2))
88 self
.mid
= Signal(self
.mmax
, reset_less
=True) # multiplex id
89 for i
in range(num_rows
):
90 self
.rs
.append(FPGetSyncOpsMod(width
, num_ops
))
91 self
.rs
= Array(self
.rs
)
93 self
.out_op
= FPOps(width
, num_ops
)
95 def elaborate(self
, platform
):
98 pe
= PriorityEncoder(self
.num_rows
)
99 m
.submodules
.selector
= pe
100 m
.submodules
.out_op
= self
.out_op
101 m
.submodules
+= self
.rs
103 # connect priority encoder
105 for i
in range(self
.num_rows
):
106 in_ready
.append(self
.rs
[i
].ready
)
107 m
.d
.comb
+= pe
.i
.eq(Cat(*in_ready
))
109 active
= Signal(reset_less
=True)
110 out_en
= Signal(reset_less
=True)
111 m
.d
.comb
+= active
.eq(~pe
.n
) # encoder active
112 m
.d
.comb
+= out_en
.eq(active
& self
.out_op
.trigger
)
114 # encoder active: ack relevant input, record MID, pass output
117 m
.d
.sync
+= self
.mid
.eq(pe
.o
)
118 m
.d
.sync
+= rs
.ack
.eq(0)
119 m
.d
.sync
+= self
.out_op
.stb
.eq(0)
120 for j
in range(self
.num_ops
):
121 m
.d
.sync
+= self
.out_op
.v
[j
].eq(rs
.out_op
[j
])
123 m
.d
.sync
+= self
.out_op
.stb
.eq(1)
124 # acks all default to zero
125 for i
in range(self
.num_rows
):
126 m
.d
.sync
+= self
.rs
[i
].ack
.eq(1)
132 for i
in range(self
.num_rows
):
134 res
+= inop
.in_op
+ [inop
.stb
]
135 return self
.out_op
.ports() + res
+ [self
.mid
]
139 def __init__(self
, width
):
140 self
.in_op
= FPOp(width
)
141 self
.out_op
= Signal(width
)
142 self
.out_decode
= Signal(reset_less
=True)
144 def elaborate(self
, platform
):
146 m
.d
.comb
+= self
.out_decode
.eq((self
.in_op
.ack
) & (self
.in_op
.stb
))
147 m
.submodules
.get_op_in
= self
.in_op
148 #m.submodules.get_op_out = self.out_op
149 with m
.If(self
.out_decode
):
151 self
.out_op
.eq(self
.in_op
.v
),
156 class FPGetOp(FPState
):
160 def __init__(self
, in_state
, out_state
, in_op
, width
):
161 FPState
.__init
__(self
, in_state
)
162 self
.out_state
= out_state
163 self
.mod
= FPGetOpMod(width
)
165 self
.out_op
= Signal(width
)
166 self
.out_decode
= Signal(reset_less
=True)
168 def setup(self
, m
, in_op
):
169 """ links module to inputs and outputs
171 setattr(m
.submodules
, self
.state_from
, self
.mod
)
172 m
.d
.comb
+= self
.mod
.in_op
.eq(in_op
)
173 #m.d.comb += self.out_op.eq(self.mod.out_op)
174 m
.d
.comb
+= self
.out_decode
.eq(self
.mod
.out_decode
)
177 with m
.If(self
.out_decode
):
178 m
.next
= self
.out_state
180 self
.in_op
.ack
.eq(0),
181 self
.out_op
.eq(self
.mod
.out_op
)
184 m
.d
.sync
+= self
.in_op
.ack
.eq(1)
187 class FPGet2OpMod(Trigger
):
188 def __init__(self
, width
):
189 Trigger
.__init
__(self
)
190 self
.in_op1
= Signal(width
, reset_less
=True)
191 self
.in_op2
= Signal(width
, reset_less
=True)
192 self
.out_op1
= FPNumIn(None, width
)
193 self
.out_op2
= FPNumIn(None, width
)
195 def elaborate(self
, platform
):
196 m
= Trigger
.elaborate(self
, platform
)
197 #m.submodules.get_op_in = self.in_op
198 m
.submodules
.get_op1_out
= self
.out_op1
199 m
.submodules
.get_op2_out
= self
.out_op2
200 with m
.If(self
.trigger
):
202 self
.out_op1
.decode(self
.in_op1
),
203 self
.out_op2
.decode(self
.in_op2
),
208 class FPGet2Op(FPState
):
212 def __init__(self
, in_state
, out_state
, in_op1
, in_op2
, width
):
213 FPState
.__init
__(self
, in_state
)
214 self
.out_state
= out_state
215 self
.mod
= FPGet2OpMod(width
)
218 self
.out_op1
= FPNumIn(None, width
)
219 self
.out_op2
= FPNumIn(None, width
)
220 self
.in_stb
= Signal(reset_less
=True)
221 self
.out_ack
= Signal(reset_less
=True)
222 self
.out_decode
= Signal(reset_less
=True)
224 def setup(self
, m
, in_op1
, in_op2
, in_stb
, in_ack
):
225 """ links module to inputs and outputs
227 m
.submodules
.get_ops
= self
.mod
228 m
.d
.comb
+= self
.mod
.in_op1
.eq(in_op1
)
229 m
.d
.comb
+= self
.mod
.in_op2
.eq(in_op2
)
230 m
.d
.comb
+= self
.mod
.stb
.eq(in_stb
)
231 m
.d
.comb
+= self
.out_ack
.eq(self
.mod
.ack
)
232 m
.d
.comb
+= self
.out_decode
.eq(self
.mod
.trigger
)
233 m
.d
.comb
+= in_ack
.eq(self
.mod
.ack
)
236 with m
.If(self
.out_decode
):
237 m
.next
= self
.out_state
240 #self.out_op1.v.eq(self.mod.out_op1.v),
241 #self.out_op2.v.eq(self.mod.out_op2.v),
242 self
.out_op1
.eq(self
.mod
.out_op1
),
243 self
.out_op2
.eq(self
.mod
.out_op2
)
246 m
.d
.sync
+= self
.mod
.ack
.eq(1)
250 def __init__(self
, width
, id_wid
, m_extra
=True):
251 self
.a
= FPNumBase(width
, m_extra
)
252 self
.b
= FPNumBase(width
, m_extra
)
253 self
.mid
= Signal(id_wid
, reset_less
=True)
256 return [self
.a
.eq(i
.a
), self
.b
.eq(i
.b
), self
.mid
.eq(i
.mid
)]
259 class FPAddSpecialCasesMod
:
260 """ special cases: NaNs, infs, zeros, denormalised
261 NOTE: some of these are unique to add. see "Special Operations"
262 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
265 def __init__(self
, width
, id_wid
):
268 self
.i
= self
.ispec()
269 self
.out_z
= self
.ospec()
270 self
.out_do_z
= Signal(reset_less
=True)
273 return FPNumBase2Ops(self
.width
, self
.id_wid
)
276 return FPNumOut(self
.width
, False)
278 def setup(self
, m
, in_a
, in_b
, out_do_z
):
279 """ links module to inputs and outputs
281 m
.submodules
.specialcases
= self
282 m
.d
.comb
+= self
.i
.a
.eq(in_a
)
283 m
.d
.comb
+= self
.i
.b
.eq(in_b
)
284 m
.d
.comb
+= out_do_z
.eq(self
.out_do_z
)
286 def elaborate(self
, platform
):
289 m
.submodules
.sc_in_a
= self
.i
.a
290 m
.submodules
.sc_in_b
= self
.i
.b
291 m
.submodules
.sc_out_z
= self
.out_z
294 m
.d
.comb
+= s_nomatch
.eq(self
.i
.a
.s
!= self
.i
.b
.s
)
297 m
.d
.comb
+= m_match
.eq(self
.i
.a
.m
== self
.i
.b
.m
)
299 # if a is NaN or b is NaN return NaN
300 with m
.If(self
.i
.a
.is_nan | self
.i
.b
.is_nan
):
301 m
.d
.comb
+= self
.out_do_z
.eq(1)
302 m
.d
.comb
+= self
.out_z
.nan(0)
304 # XXX WEIRDNESS for FP16 non-canonical NaN handling
307 ## if a is zero and b is NaN return -b
308 #with m.If(a.is_zero & (a.s==0) & b.is_nan):
309 # m.d.comb += self.out_do_z.eq(1)
310 # m.d.comb += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
312 ## if b is zero and a is NaN return -a
313 #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
314 # m.d.comb += self.out_do_z.eq(1)
315 # m.d.comb += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
317 ## if a is -zero and b is NaN return -b
318 #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
319 # m.d.comb += self.out_do_z.eq(1)
320 # m.d.comb += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
322 ## if b is -zero and a is NaN return -a
323 #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
324 # m.d.comb += self.out_do_z.eq(1)
325 # m.d.comb += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
327 # if a is inf return inf (or NaN)
328 with m
.Elif(self
.i
.a
.is_inf
):
329 m
.d
.comb
+= self
.out_do_z
.eq(1)
330 m
.d
.comb
+= self
.out_z
.inf(self
.i
.a
.s
)
331 # if a is inf and signs don't match return NaN
332 with m
.If(self
.i
.b
.exp_128
& s_nomatch
):
333 m
.d
.comb
+= self
.out_z
.nan(0)
335 # if b is inf return inf
336 with m
.Elif(self
.i
.b
.is_inf
):
337 m
.d
.comb
+= self
.out_do_z
.eq(1)
338 m
.d
.comb
+= self
.out_z
.inf(self
.i
.b
.s
)
340 # if a is zero and b zero return signed-a/b
341 with m
.Elif(self
.i
.a
.is_zero
& self
.i
.b
.is_zero
):
342 m
.d
.comb
+= self
.out_do_z
.eq(1)
343 m
.d
.comb
+= self
.out_z
.create(self
.i
.a
.s
& self
.i
.b
.s
,
347 # if a is zero return b
348 with m
.Elif(self
.i
.a
.is_zero
):
349 m
.d
.comb
+= self
.out_do_z
.eq(1)
350 m
.d
.comb
+= self
.out_z
.create(self
.i
.b
.s
, self
.i
.b
.e
,
353 # if b is zero return a
354 with m
.Elif(self
.i
.b
.is_zero
):
355 m
.d
.comb
+= self
.out_do_z
.eq(1)
356 m
.d
.comb
+= self
.out_z
.create(self
.i
.a
.s
, self
.i
.a
.e
,
359 # if a equal to -b return zero (+ve zero)
360 with m
.Elif(s_nomatch
& m_match
& (self
.i
.a
.e
== self
.i
.b
.e
)):
361 m
.d
.comb
+= self
.out_do_z
.eq(1)
362 m
.d
.comb
+= self
.out_z
.zero(0)
364 # Denormalised Number checks
366 m
.d
.comb
+= self
.out_do_z
.eq(0)
372 def __init__(self
, id_wid
):
375 self
.in_mid
= Signal(id_wid
, reset_less
=True)
376 self
.out_mid
= Signal(id_wid
, reset_less
=True)
382 if self
.id_wid
is not None:
383 m
.d
.sync
+= self
.out_mid
.eq(self
.in_mid
)
386 class FPAddSpecialCases(FPState
, FPID
):
387 """ special cases: NaNs, infs, zeros, denormalised
388 NOTE: some of these are unique to add. see "Special Operations"
389 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
392 def __init__(self
, width
, id_wid
):
393 FPState
.__init
__(self
, "special_cases")
394 FPID
.__init
__(self
, id_wid
)
395 self
.mod
= FPAddSpecialCasesMod(width
)
396 self
.out_z
= self
.mod
.ospec()
397 self
.out_do_z
= Signal(reset_less
=True)
399 def setup(self
, m
, in_a
, in_b
, in_mid
):
400 """ links module to inputs and outputs
402 self
.mod
.setup(m
, in_a
, in_b
, self
.out_do_z
)
403 if self
.in_mid
is not None:
404 m
.d
.comb
+= self
.in_mid
.eq(in_mid
)
408 with m
.If(self
.out_do_z
):
409 m
.d
.sync
+= self
.out_z
.v
.eq(self
.mod
.out_z
.v
) # only take the output
412 m
.next
= "denormalise"
415 class FPAddSpecialCasesDeNorm(FPState
, FPID
):
416 """ special cases: NaNs, infs, zeros, denormalised
417 NOTE: some of these are unique to add. see "Special Operations"
418 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
421 def __init__(self
, width
, id_wid
):
422 FPState
.__init
__(self
, "special_cases")
423 FPID
.__init
__(self
, id_wid
)
424 self
.smod
= FPAddSpecialCasesMod(width
, id_wid
)
425 self
.out_z
= self
.smod
.ospec()
426 self
.out_do_z
= Signal(reset_less
=True)
428 self
.dmod
= FPAddDeNormMod(width
, id_wid
)
429 self
.o
= self
.dmod
.ospec()
431 def setup(self
, m
, in_a
, in_b
, in_mid
):
432 """ links module to inputs and outputs
434 self
.smod
.setup(m
, in_a
, in_b
, self
.out_do_z
)
435 self
.dmod
.setup(m
, in_a
, in_b
)
436 if self
.in_mid
is not None:
437 m
.d
.comb
+= self
.in_mid
.eq(in_mid
)
441 with m
.If(self
.out_do_z
):
442 m
.d
.sync
+= self
.out_z
.v
.eq(self
.smod
.out_z
.v
) # only take output
446 m
.d
.sync
+= self
.o
.a
.eq(self
.dmod
.o
.a
)
447 m
.d
.sync
+= self
.o
.b
.eq(self
.dmod
.o
.b
)
450 class FPAddDeNormMod(FPState
):
452 def __init__(self
, width
, id_wid
):
455 self
.i
= self
.ispec()
456 self
.o
= self
.ospec()
459 return FPNumBase2Ops(self
.width
, self
.id_wid
)
462 return FPNumBase2Ops(self
.width
, self
.id_wid
)
464 def setup(self
, m
, in_a
, in_b
):
465 """ links module to inputs and outputs
467 m
.submodules
.denormalise
= self
468 m
.d
.comb
+= self
.i
.a
.eq(in_a
)
469 m
.d
.comb
+= self
.i
.b
.eq(in_b
)
471 def elaborate(self
, platform
):
473 m
.submodules
.denorm_in_a
= self
.i
.a
474 m
.submodules
.denorm_in_b
= self
.i
.b
475 m
.submodules
.denorm_out_a
= self
.o
.a
476 m
.submodules
.denorm_out_b
= self
.o
.b
477 # hmmm, don't like repeating identical code
478 m
.d
.comb
+= self
.o
.a
.eq(self
.i
.a
)
479 with m
.If(self
.i
.a
.exp_n127
):
480 m
.d
.comb
+= self
.o
.a
.e
.eq(self
.i
.a
.N126
) # limit a exponent
482 m
.d
.comb
+= self
.o
.a
.m
[-1].eq(1) # set top mantissa bit
484 m
.d
.comb
+= self
.o
.b
.eq(self
.i
.b
)
485 with m
.If(self
.i
.b
.exp_n127
):
486 m
.d
.comb
+= self
.o
.b
.e
.eq(self
.i
.b
.N126
) # limit a exponent
488 m
.d
.comb
+= self
.o
.b
.m
[-1].eq(1) # set top mantissa bit
493 class FPAddDeNorm(FPState
, FPID
):
495 def __init__(self
, width
, id_wid
):
496 FPState
.__init
__(self
, "denormalise")
497 FPID
.__init
__(self
, id_wid
)
498 self
.mod
= FPAddDeNormMod(width
)
499 self
.out_a
= FPNumBase(width
)
500 self
.out_b
= FPNumBase(width
)
502 def setup(self
, m
, in_a
, in_b
, in_mid
):
503 """ links module to inputs and outputs
505 self
.mod
.setup(m
, in_a
, in_b
)
506 if self
.in_mid
is not None:
507 m
.d
.comb
+= self
.in_mid
.eq(in_mid
)
511 # Denormalised Number checks
513 m
.d
.sync
+= self
.out_a
.eq(self
.mod
.out_a
)
514 m
.d
.sync
+= self
.out_b
.eq(self
.mod
.out_b
)
517 class FPAddAlignMultiMod(FPState
):
519 def __init__(self
, width
):
520 self
.in_a
= FPNumBase(width
)
521 self
.in_b
= FPNumBase(width
)
522 self
.out_a
= FPNumIn(None, width
)
523 self
.out_b
= FPNumIn(None, width
)
524 self
.exp_eq
= Signal(reset_less
=True)
526 def elaborate(self
, platform
):
527 # This one however (single-cycle) will do the shift
532 m
.submodules
.align_in_a
= self
.in_a
533 m
.submodules
.align_in_b
= self
.in_b
534 m
.submodules
.align_out_a
= self
.out_a
535 m
.submodules
.align_out_b
= self
.out_b
537 # NOTE: this does *not* do single-cycle multi-shifting,
538 # it *STAYS* in the align state until exponents match
540 # exponent of a greater than b: shift b down
541 m
.d
.comb
+= self
.exp_eq
.eq(0)
542 m
.d
.comb
+= self
.out_a
.eq(self
.in_a
)
543 m
.d
.comb
+= self
.out_b
.eq(self
.in_b
)
544 agtb
= Signal(reset_less
=True)
545 altb
= Signal(reset_less
=True)
546 m
.d
.comb
+= agtb
.eq(self
.in_a
.e
> self
.in_b
.e
)
547 m
.d
.comb
+= altb
.eq(self
.in_a
.e
< self
.in_b
.e
)
549 m
.d
.comb
+= self
.out_b
.shift_down(self
.in_b
)
550 # exponent of b greater than a: shift a down
552 m
.d
.comb
+= self
.out_a
.shift_down(self
.in_a
)
553 # exponents equal: move to next stage.
555 m
.d
.comb
+= self
.exp_eq
.eq(1)
559 class FPAddAlignMulti(FPState
, FPID
):
561 def __init__(self
, width
, id_wid
):
562 FPID
.__init
__(self
, id_wid
)
563 FPState
.__init
__(self
, "align")
564 self
.mod
= FPAddAlignMultiMod(width
)
565 self
.out_a
= FPNumIn(None, width
)
566 self
.out_b
= FPNumIn(None, width
)
567 self
.exp_eq
= Signal(reset_less
=True)
569 def setup(self
, m
, in_a
, in_b
, in_mid
):
570 """ links module to inputs and outputs
572 m
.submodules
.align
= self
.mod
573 m
.d
.comb
+= self
.mod
.in_a
.eq(in_a
)
574 m
.d
.comb
+= self
.mod
.in_b
.eq(in_b
)
575 #m.d.comb += self.out_a.eq(self.mod.out_a)
576 #m.d.comb += self.out_b.eq(self.mod.out_b)
577 m
.d
.comb
+= self
.exp_eq
.eq(self
.mod
.exp_eq
)
578 if self
.in_mid
is not None:
579 m
.d
.comb
+= self
.in_mid
.eq(in_mid
)
583 m
.d
.sync
+= self
.out_a
.eq(self
.mod
.out_a
)
584 m
.d
.sync
+= self
.out_b
.eq(self
.mod
.out_b
)
585 with m
.If(self
.exp_eq
):
591 def __init__(self
, width
, id_wid
):
592 self
.a
= FPNumIn(None, width
)
593 self
.b
= FPNumIn(None, width
)
594 self
.mid
= Signal(id_wid
, reset_less
=True)
597 return [self
.a
.eq(i
.a
), self
.b
.eq(i
.b
), self
.mid
.eq(i
.mid
)]
600 class FPAddAlignSingleMod
:
602 def __init__(self
, width
, id_wid
):
605 self
.i
= self
.ispec()
606 self
.o
= self
.ospec()
609 return FPNumBase2Ops(self
.width
, self
.id_wid
)
612 return FPNumIn2Ops(self
.width
, self
.id_wid
)
614 def setup(self
, m
, in_a
, in_b
):
615 """ links module to inputs and outputs
617 m
.submodules
.align
= self
618 m
.d
.comb
+= self
.i
.a
.eq(in_a
)
619 m
.d
.comb
+= self
.i
.b
.eq(in_b
)
621 def elaborate(self
, platform
):
622 """ Aligns A against B or B against A, depending on which has the
623 greater exponent. This is done in a *single* cycle using
624 variable-width bit-shift
626 the shifter used here is quite expensive in terms of gates.
627 Mux A or B in (and out) into temporaries, as only one of them
628 needs to be aligned against the other
632 m
.submodules
.align_in_a
= self
.i
.a
633 m
.submodules
.align_in_b
= self
.i
.b
634 m
.submodules
.align_out_a
= self
.o
.a
635 m
.submodules
.align_out_b
= self
.o
.b
637 # temporary (muxed) input and output to be shifted
638 t_inp
= FPNumBase(self
.width
)
639 t_out
= FPNumIn(None, self
.width
)
640 espec
= (len(self
.i
.a
.e
), True)
641 msr
= MultiShiftRMerge(self
.i
.a
.m_width
, espec
)
642 m
.submodules
.align_t_in
= t_inp
643 m
.submodules
.align_t_out
= t_out
644 m
.submodules
.multishift_r
= msr
646 ediff
= Signal(espec
, reset_less
=True)
647 ediffr
= Signal(espec
, reset_less
=True)
648 tdiff
= Signal(espec
, reset_less
=True)
649 elz
= Signal(reset_less
=True)
650 egz
= Signal(reset_less
=True)
652 # connect multi-shifter to t_inp/out mantissa (and tdiff)
653 m
.d
.comb
+= msr
.inp
.eq(t_inp
.m
)
654 m
.d
.comb
+= msr
.diff
.eq(tdiff
)
655 m
.d
.comb
+= t_out
.m
.eq(msr
.m
)
656 m
.d
.comb
+= t_out
.e
.eq(t_inp
.e
+ tdiff
)
657 m
.d
.comb
+= t_out
.s
.eq(t_inp
.s
)
659 m
.d
.comb
+= ediff
.eq(self
.i
.a
.e
- self
.i
.b
.e
)
660 m
.d
.comb
+= ediffr
.eq(self
.i
.b
.e
- self
.i
.a
.e
)
661 m
.d
.comb
+= elz
.eq(self
.i
.a
.e
< self
.i
.b
.e
)
662 m
.d
.comb
+= egz
.eq(self
.i
.a
.e
> self
.i
.b
.e
)
664 # default: A-exp == B-exp, A and B untouched (fall through)
665 m
.d
.comb
+= self
.o
.a
.eq(self
.i
.a
)
666 m
.d
.comb
+= self
.o
.b
.eq(self
.i
.b
)
667 # only one shifter (muxed)
668 #m.d.comb += t_out.shift_down_multi(tdiff, t_inp)
669 # exponent of a greater than b: shift b down
671 m
.d
.comb
+= [t_inp
.eq(self
.i
.b
),
674 self
.o
.b
.s
.eq(self
.i
.b
.s
), # whoops forgot sign
676 # exponent of b greater than a: shift a down
678 m
.d
.comb
+= [t_inp
.eq(self
.i
.a
),
681 self
.o
.a
.s
.eq(self
.i
.a
.s
), # whoops forgot sign
686 class FPAddAlignSingle(FPState
, FPID
):
688 def __init__(self
, width
, id_wid
):
689 FPState
.__init
__(self
, "align")
690 FPID
.__init
__(self
, id_wid
)
691 self
.mod
= FPAddAlignSingleMod(width
, id_wid
)
692 self
.out_a
= FPNumIn(None, width
)
693 self
.out_b
= FPNumIn(None, width
)
695 def setup(self
, m
, in_a
, in_b
, in_mid
):
696 """ links module to inputs and outputs
698 self
.mod
.setup(m
, in_a
, in_b
)
699 if self
.in_mid
is not None:
700 m
.d
.comb
+= self
.in_mid
.eq(in_mid
)
704 # NOTE: could be done as comb
705 m
.d
.sync
+= self
.out_a
.eq(self
.mod
.out_a
)
706 m
.d
.sync
+= self
.out_b
.eq(self
.mod
.out_b
)
710 class FPAddAlignSingleAdd(FPState
, FPID
):
712 def __init__(self
, width
, id_wid
):
713 FPState
.__init
__(self
, "align")
714 FPID
.__init
__(self
, id_wid
)
715 self
.mod
= FPAddAlignSingleMod(width
, id_wid
)
716 self
.o
= self
.mod
.ospec()
718 self
.a0mod
= FPAddStage0Mod(width
, id_wid
)
719 self
.a0o
= self
.a0mod
.ospec()
721 self
.a1mod
= FPAddStage1Mod(width
, id_wid
)
722 self
.a1o
= self
.a1mod
.ospec()
724 def setup(self
, m
, in_a
, in_b
, in_mid
):
725 """ links module to inputs and outputs
727 self
.mod
.setup(m
, in_a
, in_b
)
728 m
.d
.comb
+= self
.o
.eq(self
.mod
.o
)
730 self
.a0mod
.setup(m
, self
.o
.a
, self
.o
.b
)
731 m
.d
.comb
+= self
.a0o
.eq(self
.a0mod
.o
)
733 self
.a1mod
.setup(m
, self
.a0o
.tot
, self
.a0o
.z
)
735 if self
.in_mid
is not None:
736 m
.d
.comb
+= self
.in_mid
.eq(in_mid
)
740 m
.d
.sync
+= self
.a1o
.eq(self
.a1mod
.o
)
741 m
.next
= "normalise_1"
744 class FPAddStage0Data
:
746 def __init__(self
, width
, id_wid
):
747 self
.z
= FPNumBase(width
, False)
748 self
.tot
= Signal(self
.z
.m_width
+ 4, reset_less
=True)
749 self
.mid
= Signal(id_wid
, reset_less
=True)
752 return [self
.z
.eq(i
.z
), self
.tot
.eq(i
.tot
), self
.mid
.eq(i
.mid
)]
755 class FPAddStage0Mod
:
757 def __init__(self
, width
, id_wid
):
760 self
.i
= self
.ispec()
761 self
.o
= self
.ospec()
764 return FPNumBase2Ops(self
.width
, self
.id_wid
)
767 return FPAddStage0Data(self
.width
, self
.id_wid
)
769 def setup(self
, m
, in_a
, in_b
):
770 """ links module to inputs and outputs
772 m
.submodules
.add0
= self
773 m
.d
.comb
+= self
.i
.a
.eq(in_a
)
774 m
.d
.comb
+= self
.i
.b
.eq(in_b
)
776 def elaborate(self
, platform
):
778 m
.submodules
.add0_in_a
= self
.i
.a
779 m
.submodules
.add0_in_b
= self
.i
.b
780 m
.submodules
.add0_out_z
= self
.o
.z
782 m
.d
.comb
+= self
.o
.z
.e
.eq(self
.i
.a
.e
)
784 # store intermediate tests (and zero-extended mantissas)
785 seq
= Signal(reset_less
=True)
786 mge
= Signal(reset_less
=True)
787 am0
= Signal(len(self
.i
.a
.m
)+1, reset_less
=True)
788 bm0
= Signal(len(self
.i
.b
.m
)+1, reset_less
=True)
789 m
.d
.comb
+= [seq
.eq(self
.i
.a
.s
== self
.i
.b
.s
),
790 mge
.eq(self
.i
.a
.m
>= self
.i
.b
.m
),
791 am0
.eq(Cat(self
.i
.a
.m
, 0)),
792 bm0
.eq(Cat(self
.i
.b
.m
, 0))
794 # same-sign (both negative or both positive) add mantissas
797 self
.o
.tot
.eq(am0
+ bm0
),
798 self
.o
.z
.s
.eq(self
.i
.a
.s
)
800 # a mantissa greater than b, use a
803 self
.o
.tot
.eq(am0
- bm0
),
804 self
.o
.z
.s
.eq(self
.i
.a
.s
)
806 # b mantissa greater than a, use b
809 self
.o
.tot
.eq(bm0
- am0
),
810 self
.o
.z
.s
.eq(self
.i
.b
.s
)
815 class FPAddStage0(FPState
, FPID
):
816 """ First stage of add. covers same-sign (add) and subtract
817 special-casing when mantissas are greater or equal, to
818 give greatest accuracy.
821 def __init__(self
, width
, id_wid
):
822 FPState
.__init
__(self
, "add_0")
823 FPID
.__init
__(self
, id_wid
)
824 self
.mod
= FPAddStage0Mod(width
)
825 self
.o
= self
.mod
.ospec()
827 def setup(self
, m
, in_a
, in_b
, in_mid
):
828 """ links module to inputs and outputs
830 self
.mod
.setup(m
, in_a
, in_b
)
831 if self
.in_mid
is not None:
832 m
.d
.comb
+= self
.in_mid
.eq(in_mid
)
836 # NOTE: these could be done as combinatorial (merge add0+add1)
837 m
.d
.sync
+= self
.o
.eq(self
.mod
.o
)
841 class FPAddStage1Data
:
843 def __init__(self
, width
, id_wid
):
844 self
.z
= FPNumBase(width
, False)
846 self
.mid
= Signal(id_wid
, reset_less
=True)
849 return [self
.z
.eq(i
.z
), self
.of
.eq(i
.of
), self
.mid
.eq(i
.mid
)]
853 class FPAddStage1Mod(FPState
):
854 """ Second stage of add: preparation for normalisation.
855 detects when tot sum is too big (tot[27] is kinda a carry bit)
858 def __init__(self
, width
, id_wid
):
861 self
.i
= self
.ispec()
862 self
.o
= self
.ospec()
865 return FPAddStage0Data(self
.width
, self
.id_wid
)
868 return FPAddStage1Data(self
.width
, self
.id_wid
)
870 def setup(self
, m
, in_tot
, in_z
):
871 """ links module to inputs and outputs
873 m
.submodules
.add1
= self
874 m
.submodules
.add1_out_overflow
= self
.o
.of
876 m
.d
.comb
+= self
.i
.z
.eq(in_z
)
877 m
.d
.comb
+= self
.i
.tot
.eq(in_tot
)
879 def elaborate(self
, platform
):
881 #m.submodules.norm1_in_overflow = self.in_of
882 #m.submodules.norm1_out_overflow = self.out_of
883 #m.submodules.norm1_in_z = self.in_z
884 #m.submodules.norm1_out_z = self.out_z
885 m
.d
.comb
+= self
.o
.z
.eq(self
.i
.z
)
886 # tot[-1] (MSB) gets set when the sum overflows. shift result down
887 with m
.If(self
.i
.tot
[-1]):
889 self
.o
.z
.m
.eq(self
.i
.tot
[4:]),
890 self
.o
.of
.m0
.eq(self
.i
.tot
[4]),
891 self
.o
.of
.guard
.eq(self
.i
.tot
[3]),
892 self
.o
.of
.round_bit
.eq(self
.i
.tot
[2]),
893 self
.o
.of
.sticky
.eq(self
.i
.tot
[1] | self
.i
.tot
[0]),
894 self
.o
.z
.e
.eq(self
.i
.z
.e
+ 1)
896 # tot[-1] (MSB) zero case
899 self
.o
.z
.m
.eq(self
.i
.tot
[3:]),
900 self
.o
.of
.m0
.eq(self
.i
.tot
[3]),
901 self
.o
.of
.guard
.eq(self
.i
.tot
[2]),
902 self
.o
.of
.round_bit
.eq(self
.i
.tot
[1]),
903 self
.o
.of
.sticky
.eq(self
.i
.tot
[0])
908 class FPAddStage1(FPState
, FPID
):
910 def __init__(self
, width
, id_wid
):
911 FPState
.__init
__(self
, "add_1")
912 FPID
.__init
__(self
, id_wid
)
913 self
.mod
= FPAddStage1Mod(width
)
914 self
.out_z
= FPNumBase(width
, False)
915 self
.out_of
= Overflow()
916 self
.norm_stb
= Signal()
918 def setup(self
, m
, in_tot
, in_z
, in_mid
):
919 """ links module to inputs and outputs
921 self
.mod
.setup(m
, in_tot
, in_z
)
923 m
.d
.sync
+= self
.norm_stb
.eq(0) # sets to zero when not in add1 state
925 if self
.in_mid
is not None:
926 m
.d
.comb
+= self
.in_mid
.eq(in_mid
)
930 m
.d
.sync
+= self
.out_of
.eq(self
.mod
.out_of
)
931 m
.d
.sync
+= self
.out_z
.eq(self
.mod
.out_z
)
932 m
.d
.sync
+= self
.norm_stb
.eq(1)
933 m
.next
= "normalise_1"
936 class FPNormaliseModSingle
:
938 def __init__(self
, width
):
940 self
.in_z
= self
.ispec()
941 self
.out_z
= self
.ospec()
944 return FPNumBase(self
.width
, False)
947 return FPNumBase(self
.width
, False)
949 def setup(self
, m
, in_z
, out_z
):
950 """ links module to inputs and outputs
952 m
.submodules
.normalise
= self
953 m
.d
.comb
+= self
.in_z
.eq(in_z
)
954 m
.d
.comb
+= out_z
.eq(self
.out_z
)
956 def elaborate(self
, platform
):
959 mwid
= self
.out_z
.m_width
+2
960 pe
= PriorityEncoder(mwid
)
961 m
.submodules
.norm_pe
= pe
963 m
.submodules
.norm1_out_z
= self
.out_z
964 m
.submodules
.norm1_in_z
= self
.in_z
966 in_z
= FPNumBase(self
.width
, False)
968 m
.submodules
.norm1_insel_z
= in_z
969 m
.submodules
.norm1_insel_overflow
= in_of
971 espec
= (len(in_z
.e
), True)
972 ediff_n126
= Signal(espec
, reset_less
=True)
973 msr
= MultiShiftRMerge(mwid
, espec
)
974 m
.submodules
.multishift_r
= msr
976 m
.d
.comb
+= in_z
.eq(self
.in_z
)
977 m
.d
.comb
+= in_of
.eq(self
.in_of
)
978 # initialise out from in (overridden below)
979 m
.d
.comb
+= self
.out_z
.eq(in_z
)
980 m
.d
.comb
+= self
.out_of
.eq(in_of
)
981 # normalisation decrease condition
982 decrease
= Signal(reset_less
=True)
983 m
.d
.comb
+= decrease
.eq(in_z
.m_msbzero
)
986 # *sigh* not entirely obvious: count leading zeros (clz)
987 # with a PriorityEncoder: to find from the MSB
988 # we reverse the order of the bits.
989 temp_m
= Signal(mwid
, reset_less
=True)
990 temp_s
= Signal(mwid
+1, reset_less
=True)
991 clz
= Signal((len(in_z
.e
), True), reset_less
=True)
993 # cat round and guard bits back into the mantissa
994 temp_m
.eq(Cat(in_of
.round_bit
, in_of
.guard
, in_z
.m
)),
995 pe
.i
.eq(temp_m
[::-1]), # inverted
996 clz
.eq(pe
.o
), # count zeros from MSB down
997 temp_s
.eq(temp_m
<< clz
), # shift mantissa UP
998 self
.out_z
.e
.eq(in_z
.e
- clz
), # DECREASE exponent
999 self
.out_z
.m
.eq(temp_s
[2:]), # exclude bits 0&1
1006 def __init__(self
, width
):
1008 self
.roundz
= Signal(reset_less
=True)
1009 self
.z
= FPNumBase(width
, False)
1012 return [self
.z
.eq(i
.z
), self
.roundz
.eq(i
.roundz
)]
1015 class FPNorm1ModSingle
:
1017 def __init__(self
, width
, id_wid
):
1019 self
.id_wid
= id_wid
1020 self
.i
= self
.ispec()
1021 self
.o
= self
.ospec()
1024 return FPAddStage1Data(self
.width
, self
.id_wid
)
1027 return FPNorm1Data(self
.width
)
1029 def setup(self
, m
, in_z
, in_of
, out_z
):
1030 """ links module to inputs and outputs
1032 m
.submodules
.normalise_1
= self
1034 m
.d
.comb
+= self
.i
.z
.eq(in_z
)
1035 m
.d
.comb
+= self
.i
.of
.eq(in_of
)
1037 m
.d
.comb
+= out_z
.eq(self
.o
.z
)
1039 def elaborate(self
, platform
):
1042 mwid
= self
.o
.z
.m_width
+2
1043 pe
= PriorityEncoder(mwid
)
1044 m
.submodules
.norm_pe
= pe
1047 m
.d
.comb
+= self
.o
.roundz
.eq(of
.roundz
)
1049 m
.submodules
.norm1_out_z
= self
.o
.z
1050 m
.submodules
.norm1_out_overflow
= of
1051 m
.submodules
.norm1_in_z
= self
.i
.z
1052 m
.submodules
.norm1_in_overflow
= self
.i
.of
1055 m
.submodules
.norm1_insel_z
= i
.z
1056 m
.submodules
.norm1_insel_overflow
= i
.of
1058 espec
= (len(i
.z
.e
), True)
1059 ediff_n126
= Signal(espec
, reset_less
=True)
1060 msr
= MultiShiftRMerge(mwid
, espec
)
1061 m
.submodules
.multishift_r
= msr
1063 m
.d
.comb
+= i
.eq(self
.i
)
1064 # initialise out from in (overridden below)
1065 m
.d
.comb
+= self
.o
.z
.eq(i
.z
)
1066 m
.d
.comb
+= of
.eq(i
.of
)
1067 # normalisation increase/decrease conditions
1068 decrease
= Signal(reset_less
=True)
1069 increase
= Signal(reset_less
=True)
1070 m
.d
.comb
+= decrease
.eq(i
.z
.m_msbzero
& i
.z
.exp_gt_n126
)
1071 m
.d
.comb
+= increase
.eq(i
.z
.exp_lt_n126
)
1073 with m
.If(decrease
):
1074 # *sigh* not entirely obvious: count leading zeros (clz)
1075 # with a PriorityEncoder: to find from the MSB
1076 # we reverse the order of the bits.
1077 temp_m
= Signal(mwid
, reset_less
=True)
1078 temp_s
= Signal(mwid
+1, reset_less
=True)
1079 clz
= Signal((len(i
.z
.e
), True), reset_less
=True)
1080 # make sure that the amount to decrease by does NOT
1081 # go below the minimum non-INF/NaN exponent
1082 limclz
= Mux(i
.z
.exp_sub_n126
> pe
.o
, pe
.o
,
1085 # cat round and guard bits back into the mantissa
1086 temp_m
.eq(Cat(i
.of
.round_bit
, i
.of
.guard
, i
.z
.m
)),
1087 pe
.i
.eq(temp_m
[::-1]), # inverted
1088 clz
.eq(limclz
), # count zeros from MSB down
1089 temp_s
.eq(temp_m
<< clz
), # shift mantissa UP
1090 self
.o
.z
.e
.eq(i
.z
.e
- clz
), # DECREASE exponent
1091 self
.o
.z
.m
.eq(temp_s
[2:]), # exclude bits 0&1
1092 of
.m0
.eq(temp_s
[2]), # copy of mantissa[0]
1093 # overflow in bits 0..1: got shifted too (leave sticky)
1094 of
.guard
.eq(temp_s
[1]), # guard
1095 of
.round_bit
.eq(temp_s
[0]), # round
1098 with m
.Elif(increase
):
1099 temp_m
= Signal(mwid
+1, reset_less
=True)
1101 temp_m
.eq(Cat(i
.of
.sticky
, i
.of
.round_bit
, i
.of
.guard
,
1103 ediff_n126
.eq(i
.z
.N126
- i
.z
.e
),
1104 # connect multi-shifter to inp/out mantissa (and ediff)
1106 msr
.diff
.eq(ediff_n126
),
1107 self
.o
.z
.m
.eq(msr
.m
[3:]),
1108 of
.m0
.eq(temp_s
[3]), # copy of mantissa[0]
1109 # overflow in bits 0..1: got shifted too (leave sticky)
1110 of
.guard
.eq(temp_s
[2]), # guard
1111 of
.round_bit
.eq(temp_s
[1]), # round
1112 of
.sticky
.eq(temp_s
[0]), # sticky
1113 self
.o
.z
.e
.eq(i
.z
.e
+ ediff_n126
),
1119 class FPNorm1ModMulti
:
1121 def __init__(self
, width
, single_cycle
=True):
1123 self
.in_select
= Signal(reset_less
=True)
1124 self
.in_z
= FPNumBase(width
, False)
1125 self
.in_of
= Overflow()
1126 self
.temp_z
= FPNumBase(width
, False)
1127 self
.temp_of
= Overflow()
1128 self
.out_z
= FPNumBase(width
, False)
1129 self
.out_of
= Overflow()
1131 def elaborate(self
, platform
):
1134 m
.submodules
.norm1_out_z
= self
.out_z
1135 m
.submodules
.norm1_out_overflow
= self
.out_of
1136 m
.submodules
.norm1_temp_z
= self
.temp_z
1137 m
.submodules
.norm1_temp_of
= self
.temp_of
1138 m
.submodules
.norm1_in_z
= self
.in_z
1139 m
.submodules
.norm1_in_overflow
= self
.in_of
1141 in_z
= FPNumBase(self
.width
, False)
1143 m
.submodules
.norm1_insel_z
= in_z
1144 m
.submodules
.norm1_insel_overflow
= in_of
1146 # select which of temp or in z/of to use
1147 with m
.If(self
.in_select
):
1148 m
.d
.comb
+= in_z
.eq(self
.in_z
)
1149 m
.d
.comb
+= in_of
.eq(self
.in_of
)
1151 m
.d
.comb
+= in_z
.eq(self
.temp_z
)
1152 m
.d
.comb
+= in_of
.eq(self
.temp_of
)
1153 # initialise out from in (overridden below)
1154 m
.d
.comb
+= self
.out_z
.eq(in_z
)
1155 m
.d
.comb
+= self
.out_of
.eq(in_of
)
1156 # normalisation increase/decrease conditions
1157 decrease
= Signal(reset_less
=True)
1158 increase
= Signal(reset_less
=True)
1159 m
.d
.comb
+= decrease
.eq(in_z
.m_msbzero
& in_z
.exp_gt_n126
)
1160 m
.d
.comb
+= increase
.eq(in_z
.exp_lt_n126
)
1161 m
.d
.comb
+= self
.out_norm
.eq(decrease | increase
) # loop-end
1163 with m
.If(decrease
):
1165 self
.out_z
.e
.eq(in_z
.e
- 1), # DECREASE exponent
1166 self
.out_z
.m
.eq(in_z
.m
<< 1), # shift mantissa UP
1167 self
.out_z
.m
[0].eq(in_of
.guard
), # steal guard (was tot[2])
1168 self
.out_of
.guard
.eq(in_of
.round_bit
), # round (was tot[1])
1169 self
.out_of
.round_bit
.eq(0), # reset round bit
1170 self
.out_of
.m0
.eq(in_of
.guard
),
1173 with m
.Elif(increase
):
1175 self
.out_z
.e
.eq(in_z
.e
+ 1), # INCREASE exponent
1176 self
.out_z
.m
.eq(in_z
.m
>> 1), # shift mantissa DOWN
1177 self
.out_of
.guard
.eq(in_z
.m
[0]),
1178 self
.out_of
.m0
.eq(in_z
.m
[1]),
1179 self
.out_of
.round_bit
.eq(in_of
.guard
),
1180 self
.out_of
.sticky
.eq(in_of
.sticky | in_of
.round_bit
)
1186 class FPNorm1Single(FPState
, FPID
):
1188 def __init__(self
, width
, id_wid
, single_cycle
=True):
1189 FPID
.__init
__(self
, id_wid
)
1190 FPState
.__init
__(self
, "normalise_1")
1191 self
.mod
= FPNorm1ModSingle(width
)
1192 self
.out_z
= FPNumBase(width
, False)
1193 self
.out_roundz
= Signal(reset_less
=True)
1195 def setup(self
, m
, in_z
, in_of
, in_mid
):
1196 """ links module to inputs and outputs
1198 self
.mod
.setup(m
, in_z
, in_of
, self
.out_z
)
1200 if self
.in_mid
is not None:
1201 m
.d
.comb
+= self
.in_mid
.eq(in_mid
)
1203 def action(self
, m
):
1205 m
.d
.sync
+= self
.out_roundz
.eq(self
.mod
.out_of
.roundz
)
1209 class FPNorm1Multi(FPState
, FPID
):
1211 def __init__(self
, width
, id_wid
):
1212 FPID
.__init
__(self
, id_wid
)
1213 FPState
.__init
__(self
, "normalise_1")
1214 self
.mod
= FPNorm1ModMulti(width
)
1215 self
.stb
= Signal(reset_less
=True)
1216 self
.ack
= Signal(reset
=0, reset_less
=True)
1217 self
.out_norm
= Signal(reset_less
=True)
1218 self
.in_accept
= Signal(reset_less
=True)
1219 self
.temp_z
= FPNumBase(width
)
1220 self
.temp_of
= Overflow()
1221 self
.out_z
= FPNumBase(width
)
1222 self
.out_roundz
= Signal(reset_less
=True)
1224 def setup(self
, m
, in_z
, in_of
, norm_stb
, in_mid
):
1225 """ links module to inputs and outputs
1227 self
.mod
.setup(m
, in_z
, in_of
, norm_stb
,
1228 self
.in_accept
, self
.temp_z
, self
.temp_of
,
1229 self
.out_z
, self
.out_norm
)
1231 m
.d
.comb
+= self
.stb
.eq(norm_stb
)
1232 m
.d
.sync
+= self
.ack
.eq(0) # sets to zero when not in normalise_1 state
1234 if self
.in_mid
is not None:
1235 m
.d
.comb
+= self
.in_mid
.eq(in_mid
)
1237 def action(self
, m
):
1239 m
.d
.comb
+= self
.in_accept
.eq((~self
.ack
) & (self
.stb
))
1240 m
.d
.sync
+= self
.temp_of
.eq(self
.mod
.out_of
)
1241 m
.d
.sync
+= self
.temp_z
.eq(self
.out_z
)
1242 with m
.If(self
.out_norm
):
1243 with m
.If(self
.in_accept
):
1248 m
.d
.sync
+= self
.ack
.eq(0)
1250 # normalisation not required (or done).
1252 m
.d
.sync
+= self
.ack
.eq(1)
1253 m
.d
.sync
+= self
.out_roundz
.eq(self
.mod
.out_of
.roundz
)
1256 class FPNormToPack(FPState
, FPID
):
1258 def __init__(self
, width
, id_wid
):
1259 FPID
.__init
__(self
, id_wid
)
1260 FPState
.__init
__(self
, "normalise_1")
1263 def setup(self
, m
, in_z
, in_of
, in_mid
):
1264 """ links module to inputs and outputs
1267 # Normalisation (chained to input in_z+in_of)
1268 nmod
= FPNorm1ModSingle(self
.width
, self
.id_wid
)
1269 n_out
= nmod
.ospec()
1270 nmod
.setup(m
, in_z
, in_of
, n_out
.z
)
1271 m
.d
.comb
+= n_out
.roundz
.eq(nmod
.o
.roundz
)
1273 # Rounding (chained to normalisation)
1274 rmod
= FPRoundMod(self
.width
)
1275 r_out_z
= rmod
.ospec()
1276 rmod
.setup(m
, n_out
.z
, n_out
.roundz
)
1277 m
.d
.comb
+= r_out_z
.eq(rmod
.out_z
)
1279 # Corrections (chained to rounding)
1280 cmod
= FPCorrectionsMod(self
.width
)
1281 c_out_z
= cmod
.ospec()
1282 cmod
.setup(m
, r_out_z
)
1283 m
.d
.comb
+= c_out_z
.eq(cmod
.out_z
)
1285 # Pack (chained to corrections)
1286 self
.pmod
= FPPackMod(self
.width
)
1287 self
.out_z
= self
.pmod
.ospec()
1288 self
.pmod
.setup(m
, c_out_z
)
1291 if self
.in_mid
is not None:
1292 m
.d
.comb
+= self
.in_mid
.eq(in_mid
)
1294 def action(self
, m
):
1295 self
.idsync(m
) # copies incoming ID to outgoing
1296 m
.d
.sync
+= self
.out_z
.v
.eq(self
.pmod
.out_z
.v
) # outputs packed result
1297 m
.next
= "pack_put_z"
1302 def __init__(self
, width
):
1304 self
.i
= self
.ispec()
1305 self
.out_z
= self
.ospec()
1308 return FPNorm1Data(self
.width
)
1311 return FPNumBase(self
.width
, False)
1313 def setup(self
, m
, in_z
, roundz
):
1314 m
.submodules
.roundz
= self
1316 m
.d
.comb
+= self
.i
.z
.eq(in_z
)
1317 m
.d
.comb
+= self
.i
.roundz
.eq(roundz
)
1319 def elaborate(self
, platform
):
1321 m
.d
.comb
+= self
.out_z
.eq(self
.i
.z
)
1322 with m
.If(self
.i
.roundz
):
1323 m
.d
.comb
+= self
.out_z
.m
.eq(self
.i
.z
.m
+ 1) # mantissa rounds up
1324 with m
.If(self
.i
.z
.m
== self
.i
.z
.m1s
): # all 1s
1325 m
.d
.comb
+= self
.out_z
.e
.eq(self
.i
.z
.e
+ 1) # exponent up
1329 class FPRound(FPState
, FPID
):
1331 def __init__(self
, width
, id_wid
):
1332 FPState
.__init
__(self
, "round")
1333 FPID
.__init
__(self
, id_wid
)
1334 self
.mod
= FPRoundMod(width
)
1335 self
.out_z
= self
.mod
.ospec()
1337 def setup(self
, m
, in_z
, roundz
, in_mid
):
1338 """ links module to inputs and outputs
1340 self
.mod
.setup(m
, in_z
, roundz
)
1342 if self
.in_mid
is not None:
1343 m
.d
.comb
+= self
.in_mid
.eq(in_mid
)
1345 def action(self
, m
):
1347 m
.d
.sync
+= self
.out_z
.eq(self
.mod
.out_z
)
1348 m
.next
= "corrections"
1351 class FPCorrectionsMod
:
1353 def __init__(self
, width
):
1355 self
.in_z
= self
.ispec()
1356 self
.out_z
= self
.ospec()
1359 return FPNumOut(self
.width
, False)
1362 return FPNumOut(self
.width
, False)
1364 def setup(self
, m
, in_z
):
1365 """ links module to inputs and outputs
1367 m
.submodules
.corrections
= self
1368 m
.d
.comb
+= self
.in_z
.eq(in_z
)
1370 def elaborate(self
, platform
):
1372 m
.submodules
.corr_in_z
= self
.in_z
1373 m
.submodules
.corr_out_z
= self
.out_z
1374 m
.d
.comb
+= self
.out_z
.eq(self
.in_z
)
1375 with m
.If(self
.in_z
.is_denormalised
):
1376 m
.d
.comb
+= self
.out_z
.e
.eq(self
.in_z
.N127
)
1380 class FPCorrections(FPState
, FPID
):
1382 def __init__(self
, width
, id_wid
):
1383 FPState
.__init
__(self
, "corrections")
1384 FPID
.__init
__(self
, id_wid
)
1385 self
.mod
= FPCorrectionsMod(width
)
1386 self
.out_z
= self
.mod
.ospec()
1388 def setup(self
, m
, in_z
, in_mid
):
1389 """ links module to inputs and outputs
1391 self
.mod
.setup(m
, in_z
)
1392 if self
.in_mid
is not None:
1393 m
.d
.comb
+= self
.in_mid
.eq(in_mid
)
1395 def action(self
, m
):
1397 m
.d
.sync
+= self
.out_z
.eq(self
.mod
.out_z
)
1403 def __init__(self
, width
):
1405 self
.in_z
= self
.ispec()
1406 self
.out_z
= self
.ospec()
1409 return FPNumOut(self
.width
, False)
1412 return FPNumOut(self
.width
, False)
1414 def setup(self
, m
, in_z
):
1415 """ links module to inputs and outputs
1417 m
.submodules
.pack
= self
1418 m
.d
.comb
+= self
.in_z
.eq(in_z
)
1420 def elaborate(self
, platform
):
1422 m
.submodules
.pack_in_z
= self
.in_z
1423 with m
.If(self
.in_z
.is_overflowed
):
1424 m
.d
.comb
+= self
.out_z
.inf(self
.in_z
.s
)
1426 m
.d
.comb
+= self
.out_z
.create(self
.in_z
.s
, self
.in_z
.e
, self
.in_z
.m
)
1431 def __init__(self
, width
, id_wid
):
1432 self
.z
= FPNumOut(width
, False)
1433 self
.mid
= Signal(id_wid
, reset_less
=True)
1436 return [self
.z
.eq(i
.z
), self
.mid
.eq(i
.mid
)]
1439 class FPPack(FPState
, FPID
):
1441 def __init__(self
, width
, id_wid
):
1442 FPState
.__init
__(self
, "pack")
1443 FPID
.__init
__(self
, id_wid
)
1444 self
.mod
= FPPackMod(width
)
1445 self
.out_z
= self
.ospec()
1448 return self
.mod
.ispec()
1451 return self
.mod
.ospec()
1453 def setup(self
, m
, in_z
, in_mid
):
1454 """ links module to inputs and outputs
1456 self
.mod
.setup(m
, in_z
)
1457 if self
.in_mid
is not None:
1458 m
.d
.comb
+= self
.in_mid
.eq(in_mid
)
1460 def action(self
, m
):
1462 m
.d
.sync
+= self
.out_z
.v
.eq(self
.mod
.out_z
.v
)
1463 m
.next
= "pack_put_z"
1466 class FPPutZ(FPState
):
1468 def __init__(self
, state
, in_z
, out_z
, in_mid
, out_mid
, to_state
=None):
1469 FPState
.__init
__(self
, state
)
1470 if to_state
is None:
1471 to_state
= "get_ops"
1472 self
.to_state
= to_state
1475 self
.in_mid
= in_mid
1476 self
.out_mid
= out_mid
1478 def action(self
, m
):
1479 if self
.in_mid
is not None:
1480 m
.d
.sync
+= self
.out_mid
.eq(self
.in_mid
)
1482 self
.out_z
.v
.eq(self
.in_z
.v
)
1484 with m
.If(self
.out_z
.stb
& self
.out_z
.ack
):
1485 m
.d
.sync
+= self
.out_z
.stb
.eq(0)
1486 m
.next
= self
.to_state
1488 m
.d
.sync
+= self
.out_z
.stb
.eq(1)
1491 class FPPutZIdx(FPState
):
1493 def __init__(self
, state
, in_z
, out_zs
, in_mid
, to_state
=None):
1494 FPState
.__init
__(self
, state
)
1495 if to_state
is None:
1496 to_state
= "get_ops"
1497 self
.to_state
= to_state
1499 self
.out_zs
= out_zs
1500 self
.in_mid
= in_mid
1502 def action(self
, m
):
1503 outz_stb
= Signal(reset_less
=True)
1504 outz_ack
= Signal(reset_less
=True)
1505 m
.d
.comb
+= [outz_stb
.eq(self
.out_zs
[self
.in_mid
].stb
),
1506 outz_ack
.eq(self
.out_zs
[self
.in_mid
].ack
),
1509 self
.out_zs
[self
.in_mid
].v
.eq(self
.in_z
.v
)
1511 with m
.If(outz_stb
& outz_ack
):
1512 m
.d
.sync
+= self
.out_zs
[self
.in_mid
].stb
.eq(0)
1513 m
.next
= self
.to_state
1515 m
.d
.sync
+= self
.out_zs
[self
.in_mid
].stb
.eq(1)
1518 class FPADDBaseMod(FPID
):
1520 def __init__(self
, width
, id_wid
=None, single_cycle
=False, compact
=True):
1523 * width: bit-width of IEEE754. supported: 16, 32, 64
1524 * id_wid: an identifier that is sync-connected to the input
1525 * single_cycle: True indicates each stage to complete in 1 clock
1526 * compact: True indicates a reduced number of stages
1528 FPID
.__init
__(self
, id_wid
)
1530 self
.single_cycle
= single_cycle
1531 self
.compact
= compact
1533 self
.in_t
= Trigger()
1534 self
.in_a
= Signal(width
)
1535 self
.in_b
= Signal(width
)
1536 self
.out_z
= FPOp(width
)
1540 def add_state(self
, state
):
1541 self
.states
.append(state
)
1544 def get_fragment(self
, platform
=None):
1545 """ creates the HDL code-fragment for FPAdd
1548 m
.submodules
.out_z
= self
.out_z
1549 m
.submodules
.in_t
= self
.in_t
1551 self
.get_compact_fragment(m
, platform
)
1553 self
.get_longer_fragment(m
, platform
)
1555 with m
.FSM() as fsm
:
1557 for state
in self
.states
:
1558 with m
.State(state
.state_from
):
1563 def get_longer_fragment(self
, m
, platform
=None):
1565 get
= self
.add_state(FPGet2Op("get_ops", "special_cases",
1566 self
.in_a
, self
.in_b
, self
.width
))
1567 get
.setup(m
, self
.in_a
, self
.in_b
, self
.in_t
.stb
, self
.in_t
.ack
)
1571 sc
= self
.add_state(FPAddSpecialCases(self
.width
, self
.id_wid
))
1572 sc
.setup(m
, a
, b
, self
.in_mid
)
1574 dn
= self
.add_state(FPAddDeNorm(self
.width
, self
.id_wid
))
1575 dn
.setup(m
, a
, b
, sc
.in_mid
)
1577 if self
.single_cycle
:
1578 alm
= self
.add_state(FPAddAlignSingle(self
.width
, self
.id_wid
))
1579 alm
.setup(m
, dn
.out_a
, dn
.out_b
, dn
.in_mid
)
1581 alm
= self
.add_state(FPAddAlignMulti(self
.width
, self
.id_wid
))
1582 alm
.setup(m
, dn
.out_a
, dn
.out_b
, dn
.in_mid
)
1584 add0
= self
.add_state(FPAddStage0(self
.width
, self
.id_wid
))
1585 add0
.setup(m
, alm
.out_a
, alm
.out_b
, alm
.in_mid
)
1587 add1
= self
.add_state(FPAddStage1(self
.width
, self
.id_wid
))
1588 add1
.setup(m
, add0
.out_tot
, add0
.out_z
, add0
.in_mid
)
1590 if self
.single_cycle
:
1591 n1
= self
.add_state(FPNorm1Single(self
.width
, self
.id_wid
))
1592 n1
.setup(m
, add1
.out_z
, add1
.out_of
, add0
.in_mid
)
1594 n1
= self
.add_state(FPNorm1Multi(self
.width
, self
.id_wid
))
1595 n1
.setup(m
, add1
.out_z
, add1
.out_of
, add1
.norm_stb
, add0
.in_mid
)
1597 rn
= self
.add_state(FPRound(self
.width
, self
.id_wid
))
1598 rn
.setup(m
, n1
.out_z
, n1
.out_roundz
, n1
.in_mid
)
1600 cor
= self
.add_state(FPCorrections(self
.width
, self
.id_wid
))
1601 cor
.setup(m
, rn
.out_z
, rn
.in_mid
)
1603 pa
= self
.add_state(FPPack(self
.width
, self
.id_wid
))
1604 pa
.setup(m
, cor
.out_z
, rn
.in_mid
)
1606 ppz
= self
.add_state(FPPutZ("pack_put_z", pa
.out_z
, self
.out_z
,
1607 pa
.in_mid
, self
.out_mid
))
1609 pz
= self
.add_state(FPPutZ("put_z", sc
.out_z
, self
.out_z
,
1610 pa
.in_mid
, self
.out_mid
))
1612 def get_compact_fragment(self
, m
, platform
=None):
1614 get
= self
.add_state(FPGet2Op("get_ops", "special_cases",
1615 self
.in_a
, self
.in_b
, self
.width
))
1616 get
.setup(m
, self
.in_a
, self
.in_b
, self
.in_t
.stb
, self
.in_t
.ack
)
1620 sc
= self
.add_state(FPAddSpecialCasesDeNorm(self
.width
, self
.id_wid
))
1621 sc
.setup(m
, a
, b
, self
.in_mid
)
1623 alm
= self
.add_state(FPAddAlignSingleAdd(self
.width
, self
.id_wid
))
1624 alm
.setup(m
, sc
.o
.a
, sc
.o
.b
, sc
.in_mid
)
1626 n1
= self
.add_state(FPNormToPack(self
.width
, self
.id_wid
))
1627 n1
.setup(m
, alm
.a1o
.z
, alm
.a1o
.of
, alm
.in_mid
)
1629 ppz
= self
.add_state(FPPutZ("pack_put_z", n1
.out_z
, self
.out_z
,
1630 n1
.in_mid
, self
.out_mid
))
1632 pz
= self
.add_state(FPPutZ("put_z", sc
.out_z
, self
.out_z
,
1633 sc
.in_mid
, self
.out_mid
))
1636 class FPADDBase(FPState
, FPID
):
1638 def __init__(self
, width
, id_wid
=None, single_cycle
=False):
1641 * width: bit-width of IEEE754. supported: 16, 32, 64
1642 * id_wid: an identifier that is sync-connected to the input
1643 * single_cycle: True indicates each stage to complete in 1 clock
1645 FPID
.__init
__(self
, id_wid
)
1646 FPState
.__init
__(self
, "fpadd")
1648 self
.single_cycle
= single_cycle
1649 self
.mod
= FPADDBaseMod(width
, id_wid
, single_cycle
)
1651 self
.in_t
= Trigger()
1652 self
.in_a
= Signal(width
)
1653 self
.in_b
= Signal(width
)
1654 #self.out_z = FPOp(width)
1656 self
.z_done
= Signal(reset_less
=True) # connects to out_z Strobe
1657 self
.in_accept
= Signal(reset_less
=True)
1658 self
.add_stb
= Signal(reset_less
=True)
1659 self
.add_ack
= Signal(reset
=0, reset_less
=True)
1661 def setup(self
, m
, a
, b
, add_stb
, in_mid
, out_z
, out_mid
):
1663 self
.out_mid
= out_mid
1664 m
.d
.comb
+= [self
.in_a
.eq(a
),
1666 self
.mod
.in_a
.eq(self
.in_a
),
1667 self
.mod
.in_b
.eq(self
.in_b
),
1668 self
.in_mid
.eq(in_mid
),
1669 self
.mod
.in_mid
.eq(self
.in_mid
),
1670 self
.z_done
.eq(self
.mod
.out_z
.trigger
),
1671 #self.add_stb.eq(add_stb),
1672 self
.mod
.in_t
.stb
.eq(self
.in_t
.stb
),
1673 self
.in_t
.ack
.eq(self
.mod
.in_t
.ack
),
1674 self
.out_mid
.eq(self
.mod
.out_mid
),
1675 self
.out_z
.v
.eq(self
.mod
.out_z
.v
),
1676 self
.out_z
.stb
.eq(self
.mod
.out_z
.stb
),
1677 self
.mod
.out_z
.ack
.eq(self
.out_z
.ack
),
1680 m
.d
.sync
+= self
.add_stb
.eq(add_stb
)
1681 m
.d
.sync
+= self
.add_ack
.eq(0) # sets to zero when not in active state
1682 m
.d
.sync
+= self
.out_z
.ack
.eq(0) # likewise
1683 #m.d.sync += self.in_t.stb.eq(0)
1685 m
.submodules
.fpadd
= self
.mod
1687 def action(self
, m
):
1689 # in_accept is set on incoming strobe HIGH and ack LOW.
1690 m
.d
.comb
+= self
.in_accept
.eq((~self
.add_ack
) & (self
.add_stb
))
1692 #with m.If(self.in_t.ack):
1693 # m.d.sync += self.in_t.stb.eq(0)
1694 with m
.If(~self
.z_done
):
1695 # not done: test for accepting an incoming operand pair
1696 with m
.If(self
.in_accept
):
1698 self
.add_ack
.eq(1), # acknowledge receipt...
1699 self
.in_t
.stb
.eq(1), # initiate add
1702 m
.d
.sync
+= [self
.add_ack
.eq(0),
1703 self
.in_t
.stb
.eq(0),
1704 self
.out_z
.ack
.eq(1),
1707 # done: acknowledge, and write out id and value
1708 m
.d
.sync
+= [self
.add_ack
.eq(1),
1715 if self
.in_mid
is not None:
1716 m
.d
.sync
+= self
.out_mid
.eq(self
.mod
.out_mid
)
1719 self
.out_z
.v
.eq(self
.mod
.out_z
.v
)
1721 # move to output state on detecting z ack
1722 with m
.If(self
.out_z
.trigger
):
1723 m
.d
.sync
+= self
.out_z
.stb
.eq(0)
1726 m
.d
.sync
+= self
.out_z
.stb
.eq(1)
1729 def __init__(self
, width
, id_wid
):
1731 self
.id_wid
= id_wid
1733 for i
in range(rs_sz
):
1735 out_z
.name
= "out_z_%d" % i
1737 self
.res
= Array(res
)
1738 self
.in_z
= FPOp(width
)
1739 self
.in_mid
= Signal(self
.id_wid
, reset_less
=True)
1741 def setup(self
, m
, in_z
, in_mid
):
1742 m
.d
.comb
+= [self
.in_z
.eq(in_z
),
1743 self
.in_mid
.eq(in_mid
)]
1745 def get_fragment(self
, platform
=None):
1746 """ creates the HDL code-fragment for FPAdd
1749 m
.submodules
.res_in_z
= self
.in_z
1750 m
.submodules
+= self
.res
1762 """ FPADD: stages as follows:
1768 FPAddBase---> FPAddBaseMod
1770 PutZ GetOps->Specials->Align->Add1/2->Norm->Round/Pack->PutZ
1772 FPAddBase is tricky: it is both a stage and *has* stages.
1773 Connection to FPAddBaseMod therefore requires an in stb/ack
1774 and an out stb/ack. Just as with Add1-Norm1 interaction, FPGetOp
1775 needs to be the thing that raises the incoming stb.
1778 def __init__(self
, width
, id_wid
=None, single_cycle
=False, rs_sz
=2):
1781 * width: bit-width of IEEE754. supported: 16, 32, 64
1782 * id_wid: an identifier that is sync-connected to the input
1783 * single_cycle: True indicates each stage to complete in 1 clock
1786 self
.id_wid
= id_wid
1787 self
.single_cycle
= single_cycle
1789 #self.out_z = FPOp(width)
1790 self
.ids
= FPID(id_wid
)
1793 for i
in range(rs_sz
):
1796 in_a
.name
= "in_a_%d" % i
1797 in_b
.name
= "in_b_%d" % i
1798 rs
.append((in_a
, in_b
))
1802 for i
in range(rs_sz
):
1804 out_z
.name
= "out_z_%d" % i
1806 self
.res
= Array(res
)
1810 def add_state(self
, state
):
1811 self
.states
.append(state
)
1814 def get_fragment(self
, platform
=None):
1815 """ creates the HDL code-fragment for FPAdd
1818 m
.submodules
+= self
.rs
1820 in_a
= self
.rs
[0][0]
1821 in_b
= self
.rs
[0][1]
1823 out_z
= FPOp(self
.width
)
1824 out_mid
= Signal(self
.id_wid
, reset_less
=True)
1825 m
.submodules
.out_z
= out_z
1827 geta
= self
.add_state(FPGetOp("get_a", "get_b",
1832 getb
= self
.add_state(FPGetOp("get_b", "fpadd",
1837 ab
= FPADDBase(self
.width
, self
.id_wid
, self
.single_cycle
)
1838 ab
= self
.add_state(ab
)
1839 ab
.setup(m
, a
, b
, getb
.out_decode
, self
.ids
.in_mid
,
1842 pz
= self
.add_state(FPPutZIdx("put_z", ab
.out_z
, self
.res
,
1845 with m
.FSM() as fsm
:
1847 for state
in self
.states
:
1848 with m
.State(state
.state_from
):
1854 if __name__
== "__main__":
1856 alu
= FPADD(width
=32, id_wid
=5, single_cycle
=True)
1857 main(alu
, ports
=alu
.rs
[0][0].ports() + \
1858 alu
.rs
[0][1].ports() + \
1859 alu
.res
[0].ports() + \
1860 [alu
.ids
.in_mid
, alu
.ids
.out_mid
])
1862 alu
= FPADDBase(width
=32, id_wid
=5, single_cycle
=True)
1863 main(alu
, ports
=[alu
.in_a
, alu
.in_b
] + \
1864 alu
.in_t
.ports() + \
1865 alu
.out_z
.ports() + \
1866 [alu
.in_mid
, alu
.out_mid
])
1869 # works... but don't use, just do "python fname.py convert -t v"
1870 #print (verilog.convert(alu, ports=[
1871 # ports=alu.in_a.ports() + \
1872 # alu.in_b.ports() + \
1873 # alu.out_z.ports())