1808827c17d9039b773d9ba8b891113d8471a973
1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
5 from nmigen
import Module
, Signal
, Cat
, Mux
, Array
, Const
6 from nmigen
.lib
.coding
import PriorityEncoder
7 from nmigen
.cli
import main
, verilog
10 from fpbase
import FPNumIn
, FPNumOut
, FPOp
, Overflow
, FPBase
, FPNumBase
11 from fpbase
import MultiShiftRMerge
, Trigger
12 #from fpbase import FPNumShiftMultiRight
15 class FPState(FPBase
):
16 def __init__(self
, state_from
):
17 self
.state_from
= state_from
19 def set_inputs(self
, inputs
):
21 for k
,v
in inputs
.items():
24 def set_outputs(self
, outputs
):
25 self
.outputs
= outputs
26 for k
,v
in outputs
.items():
30 class FPGetSyncOpsMod
:
31 def __init__(self
, width
, num_ops
=2):
33 self
.num_ops
= num_ops
36 for i
in range(num_ops
):
37 inops
.append(Signal(width
, reset_less
=True))
38 outops
.append(Signal(width
, reset_less
=True))
41 self
.stb
= Signal(num_ops
)
43 self
.ready
= Signal(reset_less
=True)
44 self
.out_decode
= Signal(reset_less
=True)
46 def elaborate(self
, platform
):
48 m
.d
.comb
+= self
.ready
.eq(self
.stb
== Const(-1, (self
.num_ops
, False)))
49 m
.d
.comb
+= self
.out_decode
.eq(self
.ack
& self
.ready
)
50 with m
.If(self
.out_decode
):
51 for i
in range(self
.num_ops
):
53 self
.out_op
[i
].eq(self
.in_op
[i
]),
58 return self
.in_op
+ self
.out_op
+ [self
.stb
, self
.ack
]
62 def __init__(self
, width
, num_ops
):
63 Trigger
.__init
__(self
)
65 self
.num_ops
= num_ops
68 for i
in range(num_ops
):
69 res
.append(Signal(width
))
74 for i
in range(self
.num_ops
):
82 def __init__(self
, width
, num_ops
=2, num_rows
=4):
84 self
.num_ops
= num_ops
85 self
.num_rows
= num_rows
86 self
.mmax
= int(log(self
.num_rows
) / log(2))
88 self
.mid
= Signal(self
.mmax
, reset_less
=True) # multiplex id
89 for i
in range(num_rows
):
90 self
.rs
.append(FPGetSyncOpsMod(width
, num_ops
))
91 self
.rs
= Array(self
.rs
)
93 self
.out_op
= FPOps(width
, num_ops
)
95 def elaborate(self
, platform
):
98 pe
= PriorityEncoder(self
.num_rows
)
99 m
.submodules
.selector
= pe
100 m
.submodules
.out_op
= self
.out_op
101 m
.submodules
+= self
.rs
103 # connect priority encoder
105 for i
in range(self
.num_rows
):
106 in_ready
.append(self
.rs
[i
].ready
)
107 m
.d
.comb
+= pe
.i
.eq(Cat(*in_ready
))
109 active
= Signal(reset_less
=True)
110 out_en
= Signal(reset_less
=True)
111 m
.d
.comb
+= active
.eq(~pe
.n
) # encoder active
112 m
.d
.comb
+= out_en
.eq(active
& self
.out_op
.trigger
)
114 # encoder active: ack relevant input, record MID, pass output
117 m
.d
.sync
+= self
.mid
.eq(pe
.o
)
118 m
.d
.sync
+= rs
.ack
.eq(0)
119 m
.d
.sync
+= self
.out_op
.stb
.eq(0)
120 for j
in range(self
.num_ops
):
121 m
.d
.sync
+= self
.out_op
.v
[j
].eq(rs
.out_op
[j
])
123 m
.d
.sync
+= self
.out_op
.stb
.eq(1)
124 # acks all default to zero
125 for i
in range(self
.num_rows
):
126 m
.d
.sync
+= self
.rs
[i
].ack
.eq(1)
132 for i
in range(self
.num_rows
):
134 res
+= inop
.in_op
+ [inop
.stb
]
135 return self
.out_op
.ports() + res
+ [self
.mid
]
139 def __init__(self
, width
):
140 self
.in_op
= FPOp(width
)
141 self
.out_op
= Signal(width
)
142 self
.out_decode
= Signal(reset_less
=True)
144 def elaborate(self
, platform
):
146 m
.d
.comb
+= self
.out_decode
.eq((self
.in_op
.ack
) & (self
.in_op
.stb
))
147 m
.submodules
.get_op_in
= self
.in_op
148 #m.submodules.get_op_out = self.out_op
149 with m
.If(self
.out_decode
):
151 self
.out_op
.eq(self
.in_op
.v
),
156 class FPGetOp(FPState
):
160 def __init__(self
, in_state
, out_state
, in_op
, width
):
161 FPState
.__init
__(self
, in_state
)
162 self
.out_state
= out_state
163 self
.mod
= FPGetOpMod(width
)
165 self
.out_op
= Signal(width
)
166 self
.out_decode
= Signal(reset_less
=True)
168 def setup(self
, m
, in_op
):
169 """ links module to inputs and outputs
171 setattr(m
.submodules
, self
.state_from
, self
.mod
)
172 m
.d
.comb
+= self
.mod
.in_op
.eq(in_op
)
173 #m.d.comb += self.out_op.eq(self.mod.out_op)
174 m
.d
.comb
+= self
.out_decode
.eq(self
.mod
.out_decode
)
177 with m
.If(self
.out_decode
):
178 m
.next
= self
.out_state
180 self
.in_op
.ack
.eq(0),
181 self
.out_op
.eq(self
.mod
.out_op
)
184 m
.d
.sync
+= self
.in_op
.ack
.eq(1)
187 class FPGet2OpMod(Trigger
):
188 def __init__(self
, width
):
189 Trigger
.__init
__(self
)
190 self
.in_op1
= Signal(width
, reset_less
=True)
191 self
.in_op2
= Signal(width
, reset_less
=True)
192 self
.out_op1
= FPNumIn(None, width
)
193 self
.out_op2
= FPNumIn(None, width
)
195 def elaborate(self
, platform
):
196 m
= Trigger
.elaborate(self
, platform
)
197 #m.submodules.get_op_in = self.in_op
198 m
.submodules
.get_op1_out
= self
.out_op1
199 m
.submodules
.get_op2_out
= self
.out_op2
200 with m
.If(self
.trigger
):
202 self
.out_op1
.decode(self
.in_op1
),
203 self
.out_op2
.decode(self
.in_op2
),
208 class FPGet2Op(FPState
):
212 def __init__(self
, in_state
, out_state
, in_op1
, in_op2
, width
):
213 FPState
.__init
__(self
, in_state
)
214 self
.out_state
= out_state
215 self
.mod
= FPGet2OpMod(width
)
218 self
.out_op1
= FPNumIn(None, width
)
219 self
.out_op2
= FPNumIn(None, width
)
220 self
.in_stb
= Signal(reset_less
=True)
221 self
.out_ack
= Signal(reset_less
=True)
222 self
.out_decode
= Signal(reset_less
=True)
224 def setup(self
, m
, in_op1
, in_op2
, in_stb
, in_ack
):
225 """ links module to inputs and outputs
227 m
.submodules
.get_ops
= self
.mod
228 m
.d
.comb
+= self
.mod
.in_op1
.eq(in_op1
)
229 m
.d
.comb
+= self
.mod
.in_op2
.eq(in_op2
)
230 m
.d
.comb
+= self
.mod
.stb
.eq(in_stb
)
231 m
.d
.comb
+= self
.out_ack
.eq(self
.mod
.ack
)
232 m
.d
.comb
+= self
.out_decode
.eq(self
.mod
.trigger
)
233 m
.d
.comb
+= in_ack
.eq(self
.mod
.ack
)
236 with m
.If(self
.out_decode
):
237 m
.next
= self
.out_state
240 #self.out_op1.v.eq(self.mod.out_op1.v),
241 #self.out_op2.v.eq(self.mod.out_op2.v),
242 self
.out_op1
.eq(self
.mod
.out_op1
),
243 self
.out_op2
.eq(self
.mod
.out_op2
)
246 m
.d
.sync
+= self
.mod
.ack
.eq(1)
250 def __init__(self
, width
, m_extra
=True):
251 self
.a
= FPNumBase(width
, m_extra
)
252 self
.b
= FPNumBase(width
, m_extra
)
255 return [self
.a
.eq(i
.a
), self
.a
.eq(i
.b
)]
258 class FPAddSpecialCasesMod
:
259 """ special cases: NaNs, infs, zeros, denormalised
260 NOTE: some of these are unique to add. see "Special Operations"
261 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
264 def __init__(self
, width
):
266 self
.i
= self
.ispec()
267 self
.out_z
= self
.ospec()
268 self
.out_do_z
= Signal(reset_less
=True)
271 return FPNumBase2Ops(self
.width
)
274 return FPNumOut(self
.width
, False)
276 def setup(self
, m
, in_a
, in_b
, out_do_z
):
277 """ links module to inputs and outputs
279 m
.submodules
.specialcases
= self
280 m
.d
.comb
+= self
.i
.a
.eq(in_a
)
281 m
.d
.comb
+= self
.i
.b
.eq(in_b
)
282 m
.d
.comb
+= out_do_z
.eq(self
.out_do_z
)
284 def elaborate(self
, platform
):
287 m
.submodules
.sc_in_a
= self
.i
.a
288 m
.submodules
.sc_in_b
= self
.i
.b
289 m
.submodules
.sc_out_z
= self
.out_z
292 m
.d
.comb
+= s_nomatch
.eq(self
.i
.a
.s
!= self
.i
.b
.s
)
295 m
.d
.comb
+= m_match
.eq(self
.i
.a
.m
== self
.i
.b
.m
)
297 # if a is NaN or b is NaN return NaN
298 with m
.If(self
.i
.a
.is_nan | self
.i
.b
.is_nan
):
299 m
.d
.comb
+= self
.out_do_z
.eq(1)
300 m
.d
.comb
+= self
.out_z
.nan(0)
302 # XXX WEIRDNESS for FP16 non-canonical NaN handling
305 ## if a is zero and b is NaN return -b
306 #with m.If(a.is_zero & (a.s==0) & b.is_nan):
307 # m.d.comb += self.out_do_z.eq(1)
308 # m.d.comb += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
310 ## if b is zero and a is NaN return -a
311 #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
312 # m.d.comb += self.out_do_z.eq(1)
313 # m.d.comb += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
315 ## if a is -zero and b is NaN return -b
316 #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
317 # m.d.comb += self.out_do_z.eq(1)
318 # m.d.comb += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
320 ## if b is -zero and a is NaN return -a
321 #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
322 # m.d.comb += self.out_do_z.eq(1)
323 # m.d.comb += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
325 # if a is inf return inf (or NaN)
326 with m
.Elif(self
.i
.a
.is_inf
):
327 m
.d
.comb
+= self
.out_do_z
.eq(1)
328 m
.d
.comb
+= self
.out_z
.inf(self
.i
.a
.s
)
329 # if a is inf and signs don't match return NaN
330 with m
.If(self
.i
.b
.exp_128
& s_nomatch
):
331 m
.d
.comb
+= self
.out_z
.nan(0)
333 # if b is inf return inf
334 with m
.Elif(self
.i
.b
.is_inf
):
335 m
.d
.comb
+= self
.out_do_z
.eq(1)
336 m
.d
.comb
+= self
.out_z
.inf(self
.i
.b
.s
)
338 # if a is zero and b zero return signed-a/b
339 with m
.Elif(self
.i
.a
.is_zero
& self
.i
.b
.is_zero
):
340 m
.d
.comb
+= self
.out_do_z
.eq(1)
341 m
.d
.comb
+= self
.out_z
.create(self
.i
.a
.s
& self
.i
.b
.s
,
345 # if a is zero return b
346 with m
.Elif(self
.i
.a
.is_zero
):
347 m
.d
.comb
+= self
.out_do_z
.eq(1)
348 m
.d
.comb
+= self
.out_z
.create(self
.i
.b
.s
, self
.i
.b
.e
,
351 # if b is zero return a
352 with m
.Elif(self
.i
.b
.is_zero
):
353 m
.d
.comb
+= self
.out_do_z
.eq(1)
354 m
.d
.comb
+= self
.out_z
.create(self
.i
.a
.s
, self
.i
.a
.e
,
357 # if a equal to -b return zero (+ve zero)
358 with m
.Elif(s_nomatch
& m_match
& (self
.i
.a
.e
== self
.i
.b
.e
)):
359 m
.d
.comb
+= self
.out_do_z
.eq(1)
360 m
.d
.comb
+= self
.out_z
.zero(0)
362 # Denormalised Number checks
364 m
.d
.comb
+= self
.out_do_z
.eq(0)
370 def __init__(self
, id_wid
):
373 self
.in_mid
= Signal(id_wid
, reset_less
=True)
374 self
.out_mid
= Signal(id_wid
, reset_less
=True)
380 if self
.id_wid
is not None:
381 m
.d
.sync
+= self
.out_mid
.eq(self
.in_mid
)
384 class FPAddSpecialCases(FPState
, FPID
):
385 """ special cases: NaNs, infs, zeros, denormalised
386 NOTE: some of these are unique to add. see "Special Operations"
387 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
390 def __init__(self
, width
, id_wid
):
391 FPState
.__init
__(self
, "special_cases")
392 FPID
.__init
__(self
, id_wid
)
393 self
.mod
= FPAddSpecialCasesMod(width
)
394 self
.out_z
= self
.mod
.ospec()
395 self
.out_do_z
= Signal(reset_less
=True)
397 def setup(self
, m
, in_a
, in_b
, in_mid
):
398 """ links module to inputs and outputs
400 self
.mod
.setup(m
, in_a
, in_b
, self
.out_do_z
)
401 if self
.in_mid
is not None:
402 m
.d
.comb
+= self
.in_mid
.eq(in_mid
)
406 with m
.If(self
.out_do_z
):
407 m
.d
.sync
+= self
.out_z
.v
.eq(self
.mod
.out_z
.v
) # only take the output
410 m
.next
= "denormalise"
413 class FPAddSpecialCasesDeNorm(FPState
, FPID
):
414 """ special cases: NaNs, infs, zeros, denormalised
415 NOTE: some of these are unique to add. see "Special Operations"
416 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
419 def __init__(self
, width
, id_wid
):
420 FPState
.__init
__(self
, "special_cases")
421 FPID
.__init
__(self
, id_wid
)
422 self
.smod
= FPAddSpecialCasesMod(width
)
423 self
.out_z
= self
.smod
.ospec()
424 self
.out_do_z
= Signal(reset_less
=True)
426 self
.dmod
= FPAddDeNormMod(width
)
427 self
.out_a
= FPNumBase(width
)
428 self
.out_b
= FPNumBase(width
)
430 def setup(self
, m
, in_a
, in_b
, in_mid
):
431 """ links module to inputs and outputs
433 self
.smod
.setup(m
, in_a
, in_b
, self
.out_do_z
)
434 self
.dmod
.setup(m
, in_a
, in_b
)
435 if self
.in_mid
is not None:
436 m
.d
.comb
+= self
.in_mid
.eq(in_mid
)
440 with m
.If(self
.out_do_z
):
441 m
.d
.sync
+= self
.out_z
.v
.eq(self
.smod
.out_z
.v
) # only take output
445 m
.d
.sync
+= self
.out_a
.eq(self
.dmod
.o
.a
)
446 m
.d
.sync
+= self
.out_b
.eq(self
.dmod
.o
.b
)
449 class FPAddDeNormMod(FPState
):
451 def __init__(self
, width
):
453 self
.i
= self
.ispec()
454 self
.o
= self
.ospec()
457 return FPNumBase2Ops(self
.width
)
460 return FPNumBase2Ops(self
.width
)
462 def setup(self
, m
, in_a
, in_b
):
463 """ links module to inputs and outputs
465 m
.submodules
.denormalise
= self
466 m
.d
.comb
+= self
.i
.a
.eq(in_a
)
467 m
.d
.comb
+= self
.i
.b
.eq(in_b
)
469 def elaborate(self
, platform
):
471 m
.submodules
.denorm_in_a
= self
.i
.a
472 m
.submodules
.denorm_in_b
= self
.i
.b
473 m
.submodules
.denorm_out_a
= self
.o
.a
474 m
.submodules
.denorm_out_b
= self
.o
.b
475 # hmmm, don't like repeating identical code
476 m
.d
.comb
+= self
.o
.a
.eq(self
.i
.a
)
477 with m
.If(self
.i
.a
.exp_n127
):
478 m
.d
.comb
+= self
.o
.a
.e
.eq(self
.i
.a
.N126
) # limit a exponent
480 m
.d
.comb
+= self
.o
.a
.m
[-1].eq(1) # set top mantissa bit
482 m
.d
.comb
+= self
.o
.b
.eq(self
.i
.b
)
483 with m
.If(self
.i
.b
.exp_n127
):
484 m
.d
.comb
+= self
.o
.b
.e
.eq(self
.i
.b
.N126
) # limit a exponent
486 m
.d
.comb
+= self
.o
.b
.m
[-1].eq(1) # set top mantissa bit
491 class FPAddDeNorm(FPState
, FPID
):
493 def __init__(self
, width
, id_wid
):
494 FPState
.__init
__(self
, "denormalise")
495 FPID
.__init
__(self
, id_wid
)
496 self
.mod
= FPAddDeNormMod(width
)
497 self
.out_a
= FPNumBase(width
)
498 self
.out_b
= FPNumBase(width
)
500 def setup(self
, m
, in_a
, in_b
, in_mid
):
501 """ links module to inputs and outputs
503 self
.mod
.setup(m
, in_a
, in_b
)
504 if self
.in_mid
is not None:
505 m
.d
.comb
+= self
.in_mid
.eq(in_mid
)
509 # Denormalised Number checks
511 m
.d
.sync
+= self
.out_a
.eq(self
.mod
.out_a
)
512 m
.d
.sync
+= self
.out_b
.eq(self
.mod
.out_b
)
515 class FPAddAlignMultiMod(FPState
):
517 def __init__(self
, width
):
518 self
.in_a
= FPNumBase(width
)
519 self
.in_b
= FPNumBase(width
)
520 self
.out_a
= FPNumIn(None, width
)
521 self
.out_b
= FPNumIn(None, width
)
522 self
.exp_eq
= Signal(reset_less
=True)
524 def elaborate(self
, platform
):
525 # This one however (single-cycle) will do the shift
530 m
.submodules
.align_in_a
= self
.in_a
531 m
.submodules
.align_in_b
= self
.in_b
532 m
.submodules
.align_out_a
= self
.out_a
533 m
.submodules
.align_out_b
= self
.out_b
535 # NOTE: this does *not* do single-cycle multi-shifting,
536 # it *STAYS* in the align state until exponents match
538 # exponent of a greater than b: shift b down
539 m
.d
.comb
+= self
.exp_eq
.eq(0)
540 m
.d
.comb
+= self
.out_a
.eq(self
.in_a
)
541 m
.d
.comb
+= self
.out_b
.eq(self
.in_b
)
542 agtb
= Signal(reset_less
=True)
543 altb
= Signal(reset_less
=True)
544 m
.d
.comb
+= agtb
.eq(self
.in_a
.e
> self
.in_b
.e
)
545 m
.d
.comb
+= altb
.eq(self
.in_a
.e
< self
.in_b
.e
)
547 m
.d
.comb
+= self
.out_b
.shift_down(self
.in_b
)
548 # exponent of b greater than a: shift a down
550 m
.d
.comb
+= self
.out_a
.shift_down(self
.in_a
)
551 # exponents equal: move to next stage.
553 m
.d
.comb
+= self
.exp_eq
.eq(1)
557 class FPAddAlignMulti(FPState
, FPID
):
559 def __init__(self
, width
, id_wid
):
560 FPID
.__init
__(self
, id_wid
)
561 FPState
.__init
__(self
, "align")
562 self
.mod
= FPAddAlignMultiMod(width
)
563 self
.out_a
= FPNumIn(None, width
)
564 self
.out_b
= FPNumIn(None, width
)
565 self
.exp_eq
= Signal(reset_less
=True)
567 def setup(self
, m
, in_a
, in_b
, in_mid
):
568 """ links module to inputs and outputs
570 m
.submodules
.align
= self
.mod
571 m
.d
.comb
+= self
.mod
.in_a
.eq(in_a
)
572 m
.d
.comb
+= self
.mod
.in_b
.eq(in_b
)
573 #m.d.comb += self.out_a.eq(self.mod.out_a)
574 #m.d.comb += self.out_b.eq(self.mod.out_b)
575 m
.d
.comb
+= self
.exp_eq
.eq(self
.mod
.exp_eq
)
576 if self
.in_mid
is not None:
577 m
.d
.comb
+= self
.in_mid
.eq(in_mid
)
581 m
.d
.sync
+= self
.out_a
.eq(self
.mod
.out_a
)
582 m
.d
.sync
+= self
.out_b
.eq(self
.mod
.out_b
)
583 with m
.If(self
.exp_eq
):
587 class FPAddAlignSingleMod
:
589 def __init__(self
, width
):
591 self
.in_a
= FPNumBase(width
)
592 self
.in_b
= FPNumBase(width
)
593 self
.out_a
= FPNumIn(None, width
)
594 self
.out_b
= FPNumIn(None, width
)
596 def setup(self
, m
, in_a
, in_b
):
597 """ links module to inputs and outputs
599 m
.submodules
.align
= self
600 m
.d
.comb
+= self
.in_a
.eq(in_a
)
601 m
.d
.comb
+= self
.in_b
.eq(in_b
)
603 def elaborate(self
, platform
):
604 """ Aligns A against B or B against A, depending on which has the
605 greater exponent. This is done in a *single* cycle using
606 variable-width bit-shift
608 the shifter used here is quite expensive in terms of gates.
609 Mux A or B in (and out) into temporaries, as only one of them
610 needs to be aligned against the other
614 m
.submodules
.align_in_a
= self
.in_a
615 m
.submodules
.align_in_b
= self
.in_b
616 m
.submodules
.align_out_a
= self
.out_a
617 m
.submodules
.align_out_b
= self
.out_b
619 # temporary (muxed) input and output to be shifted
620 t_inp
= FPNumBase(self
.width
)
621 t_out
= FPNumIn(None, self
.width
)
622 espec
= (len(self
.in_a
.e
), True)
623 msr
= MultiShiftRMerge(self
.in_a
.m_width
, espec
)
624 m
.submodules
.align_t_in
= t_inp
625 m
.submodules
.align_t_out
= t_out
626 m
.submodules
.multishift_r
= msr
628 ediff
= Signal(espec
, reset_less
=True)
629 ediffr
= Signal(espec
, reset_less
=True)
630 tdiff
= Signal(espec
, reset_less
=True)
631 elz
= Signal(reset_less
=True)
632 egz
= Signal(reset_less
=True)
634 # connect multi-shifter to t_inp/out mantissa (and tdiff)
635 m
.d
.comb
+= msr
.inp
.eq(t_inp
.m
)
636 m
.d
.comb
+= msr
.diff
.eq(tdiff
)
637 m
.d
.comb
+= t_out
.m
.eq(msr
.m
)
638 m
.d
.comb
+= t_out
.e
.eq(t_inp
.e
+ tdiff
)
639 m
.d
.comb
+= t_out
.s
.eq(t_inp
.s
)
641 m
.d
.comb
+= ediff
.eq(self
.in_a
.e
- self
.in_b
.e
)
642 m
.d
.comb
+= ediffr
.eq(self
.in_b
.e
- self
.in_a
.e
)
643 m
.d
.comb
+= elz
.eq(self
.in_a
.e
< self
.in_b
.e
)
644 m
.d
.comb
+= egz
.eq(self
.in_a
.e
> self
.in_b
.e
)
646 # default: A-exp == B-exp, A and B untouched (fall through)
647 m
.d
.comb
+= self
.out_a
.eq(self
.in_a
)
648 m
.d
.comb
+= self
.out_b
.eq(self
.in_b
)
649 # only one shifter (muxed)
650 #m.d.comb += t_out.shift_down_multi(tdiff, t_inp)
651 # exponent of a greater than b: shift b down
653 m
.d
.comb
+= [t_inp
.eq(self
.in_b
),
655 self
.out_b
.eq(t_out
),
656 self
.out_b
.s
.eq(self
.in_b
.s
), # whoops forgot sign
658 # exponent of b greater than a: shift a down
660 m
.d
.comb
+= [t_inp
.eq(self
.in_a
),
662 self
.out_a
.eq(t_out
),
663 self
.out_a
.s
.eq(self
.in_a
.s
), # whoops forgot sign
668 class FPAddAlignSingle(FPState
, FPID
):
670 def __init__(self
, width
, id_wid
):
671 FPState
.__init
__(self
, "align")
672 FPID
.__init
__(self
, id_wid
)
673 self
.mod
= FPAddAlignSingleMod(width
)
674 self
.out_a
= FPNumIn(None, width
)
675 self
.out_b
= FPNumIn(None, width
)
677 def setup(self
, m
, in_a
, in_b
, in_mid
):
678 """ links module to inputs and outputs
680 self
.mod
.setup(m
, in_a
, in_b
)
681 if self
.in_mid
is not None:
682 m
.d
.comb
+= self
.in_mid
.eq(in_mid
)
686 # NOTE: could be done as comb
687 m
.d
.sync
+= self
.out_a
.eq(self
.mod
.out_a
)
688 m
.d
.sync
+= self
.out_b
.eq(self
.mod
.out_b
)
692 class FPAddAlignSingleAdd(FPState
, FPID
):
694 def __init__(self
, width
, id_wid
):
695 FPState
.__init
__(self
, "align")
696 FPID
.__init
__(self
, id_wid
)
697 self
.mod
= FPAddAlignSingleMod(width
)
698 self
.out_a
= FPNumIn(None, width
)
699 self
.out_b
= FPNumIn(None, width
)
701 self
.a0mod
= FPAddStage0Mod(width
)
702 self
.a0_out_z
= FPNumBase(width
, False)
703 self
.out_tot
= Signal(self
.a0_out_z
.m_width
+ 4, reset_less
=True)
704 self
.a0_out_z
= FPNumBase(width
, False)
706 self
.a1mod
= FPAddStage1Mod(width
)
707 self
.out_z
= FPNumBase(width
, False)
708 self
.out_of
= Overflow()
710 def setup(self
, m
, in_a
, in_b
, in_mid
):
711 """ links module to inputs and outputs
713 self
.mod
.setup(m
, in_a
, in_b
)
714 m
.d
.comb
+= self
.out_a
.eq(self
.mod
.out_a
)
715 m
.d
.comb
+= self
.out_b
.eq(self
.mod
.out_b
)
717 self
.a0mod
.setup(m
, self
.out_a
, self
.out_b
)
718 m
.d
.comb
+= self
.a0_out_z
.eq(self
.a0mod
.out_z
)
719 m
.d
.comb
+= self
.out_tot
.eq(self
.a0mod
.out_tot
)
721 self
.a1mod
.setup(m
, self
.out_tot
, self
.a0_out_z
)
723 if self
.in_mid
is not None:
724 m
.d
.comb
+= self
.in_mid
.eq(in_mid
)
728 m
.d
.sync
+= self
.out_of
.eq(self
.a1mod
.out_of
)
729 m
.d
.sync
+= self
.out_z
.eq(self
.a1mod
.out_z
)
730 m
.next
= "normalise_1"
733 class FPAddStage0Mod
:
735 def __init__(self
, width
):
736 self
.in_a
= FPNumBase(width
)
737 self
.in_b
= FPNumBase(width
)
738 self
.in_z
= FPNumBase(width
, False)
739 self
.out_z
= FPNumBase(width
, False)
740 self
.out_tot
= Signal(self
.out_z
.m_width
+ 4, reset_less
=True)
742 def setup(self
, m
, in_a
, in_b
):
743 """ links module to inputs and outputs
745 m
.submodules
.add0
= self
746 m
.d
.comb
+= self
.in_a
.eq(in_a
)
747 m
.d
.comb
+= self
.in_b
.eq(in_b
)
749 def elaborate(self
, platform
):
751 m
.submodules
.add0_in_a
= self
.in_a
752 m
.submodules
.add0_in_b
= self
.in_b
753 m
.submodules
.add0_out_z
= self
.out_z
755 m
.d
.comb
+= self
.out_z
.e
.eq(self
.in_a
.e
)
757 # store intermediate tests (and zero-extended mantissas)
758 seq
= Signal(reset_less
=True)
759 mge
= Signal(reset_less
=True)
760 am0
= Signal(len(self
.in_a
.m
)+1, reset_less
=True)
761 bm0
= Signal(len(self
.in_b
.m
)+1, reset_less
=True)
762 m
.d
.comb
+= [seq
.eq(self
.in_a
.s
== self
.in_b
.s
),
763 mge
.eq(self
.in_a
.m
>= self
.in_b
.m
),
764 am0
.eq(Cat(self
.in_a
.m
, 0)),
765 bm0
.eq(Cat(self
.in_b
.m
, 0))
767 # same-sign (both negative or both positive) add mantissas
770 self
.out_tot
.eq(am0
+ bm0
),
771 self
.out_z
.s
.eq(self
.in_a
.s
)
773 # a mantissa greater than b, use a
776 self
.out_tot
.eq(am0
- bm0
),
777 self
.out_z
.s
.eq(self
.in_a
.s
)
779 # b mantissa greater than a, use b
782 self
.out_tot
.eq(bm0
- am0
),
783 self
.out_z
.s
.eq(self
.in_b
.s
)
788 class FPAddStage0(FPState
, FPID
):
789 """ First stage of add. covers same-sign (add) and subtract
790 special-casing when mantissas are greater or equal, to
791 give greatest accuracy.
794 def __init__(self
, width
, id_wid
):
795 FPState
.__init
__(self
, "add_0")
796 FPID
.__init
__(self
, id_wid
)
797 self
.mod
= FPAddStage0Mod(width
)
798 self
.out_z
= FPNumBase(width
, False)
799 self
.out_tot
= Signal(self
.out_z
.m_width
+ 4, reset_less
=True)
801 def setup(self
, m
, in_a
, in_b
, in_mid
):
802 """ links module to inputs and outputs
804 self
.mod
.setup(m
, in_a
, in_b
)
805 if self
.in_mid
is not None:
806 m
.d
.comb
+= self
.in_mid
.eq(in_mid
)
810 # NOTE: these could be done as combinatorial (merge add0+add1)
811 m
.d
.sync
+= self
.out_z
.eq(self
.mod
.out_z
)
812 m
.d
.sync
+= self
.out_tot
.eq(self
.mod
.out_tot
)
816 class FPAddStage1Mod(FPState
):
817 """ Second stage of add: preparation for normalisation.
818 detects when tot sum is too big (tot[27] is kinda a carry bit)
821 def __init__(self
, width
):
822 self
.out_norm
= Signal(reset_less
=True)
823 self
.in_z
= FPNumBase(width
, False)
824 self
.in_tot
= Signal(self
.in_z
.m_width
+ 4, reset_less
=True)
825 self
.out_z
= FPNumBase(width
, False)
826 self
.out_of
= Overflow()
828 def setup(self
, m
, in_tot
, in_z
):
829 """ links module to inputs and outputs
831 m
.submodules
.add1
= self
832 m
.submodules
.add1_out_overflow
= self
.out_of
834 m
.d
.comb
+= self
.in_z
.eq(in_z
)
835 m
.d
.comb
+= self
.in_tot
.eq(in_tot
)
837 def elaborate(self
, platform
):
839 #m.submodules.norm1_in_overflow = self.in_of
840 #m.submodules.norm1_out_overflow = self.out_of
841 #m.submodules.norm1_in_z = self.in_z
842 #m.submodules.norm1_out_z = self.out_z
843 m
.d
.comb
+= self
.out_z
.eq(self
.in_z
)
844 # tot[-1] (MSB) gets set when the sum overflows. shift result down
845 with m
.If(self
.in_tot
[-1]):
847 self
.out_z
.m
.eq(self
.in_tot
[4:]),
848 self
.out_of
.m0
.eq(self
.in_tot
[4]),
849 self
.out_of
.guard
.eq(self
.in_tot
[3]),
850 self
.out_of
.round_bit
.eq(self
.in_tot
[2]),
851 self
.out_of
.sticky
.eq(self
.in_tot
[1] | self
.in_tot
[0]),
852 self
.out_z
.e
.eq(self
.in_z
.e
+ 1)
854 # tot[-1] (MSB) zero case
857 self
.out_z
.m
.eq(self
.in_tot
[3:]),
858 self
.out_of
.m0
.eq(self
.in_tot
[3]),
859 self
.out_of
.guard
.eq(self
.in_tot
[2]),
860 self
.out_of
.round_bit
.eq(self
.in_tot
[1]),
861 self
.out_of
.sticky
.eq(self
.in_tot
[0])
866 class FPAddStage1(FPState
, FPID
):
868 def __init__(self
, width
, id_wid
):
869 FPState
.__init
__(self
, "add_1")
870 FPID
.__init
__(self
, id_wid
)
871 self
.mod
= FPAddStage1Mod(width
)
872 self
.out_z
= FPNumBase(width
, False)
873 self
.out_of
= Overflow()
874 self
.norm_stb
= Signal()
876 def setup(self
, m
, in_tot
, in_z
, in_mid
):
877 """ links module to inputs and outputs
879 self
.mod
.setup(m
, in_tot
, in_z
)
881 m
.d
.sync
+= self
.norm_stb
.eq(0) # sets to zero when not in add1 state
883 if self
.in_mid
is not None:
884 m
.d
.comb
+= self
.in_mid
.eq(in_mid
)
888 m
.d
.sync
+= self
.out_of
.eq(self
.mod
.out_of
)
889 m
.d
.sync
+= self
.out_z
.eq(self
.mod
.out_z
)
890 m
.d
.sync
+= self
.norm_stb
.eq(1)
891 m
.next
= "normalise_1"
894 class FPNormaliseModSingle
:
896 def __init__(self
, width
):
898 self
.in_z
= FPNumBase(width
, False)
899 self
.out_z
= FPNumBase(width
, False)
901 def setup(self
, m
, in_z
, out_z
, modname
):
902 """ links module to inputs and outputs
904 m
.submodules
.normalise
= self
905 m
.d
.comb
+= self
.in_z
.eq(in_z
)
906 m
.d
.comb
+= out_z
.eq(self
.out_z
)
908 def elaborate(self
, platform
):
911 mwid
= self
.out_z
.m_width
+2
912 pe
= PriorityEncoder(mwid
)
913 m
.submodules
.norm_pe
= pe
915 m
.submodules
.norm1_out_z
= self
.out_z
916 m
.submodules
.norm1_in_z
= self
.in_z
918 in_z
= FPNumBase(self
.width
, False)
920 m
.submodules
.norm1_insel_z
= in_z
921 m
.submodules
.norm1_insel_overflow
= in_of
923 espec
= (len(in_z
.e
), True)
924 ediff_n126
= Signal(espec
, reset_less
=True)
925 msr
= MultiShiftRMerge(mwid
, espec
)
926 m
.submodules
.multishift_r
= msr
928 m
.d
.comb
+= in_z
.eq(self
.in_z
)
929 m
.d
.comb
+= in_of
.eq(self
.in_of
)
930 # initialise out from in (overridden below)
931 m
.d
.comb
+= self
.out_z
.eq(in_z
)
932 m
.d
.comb
+= self
.out_of
.eq(in_of
)
933 # normalisation increase/decrease conditions
934 decrease
= Signal(reset_less
=True)
935 m
.d
.comb
+= decrease
.eq(in_z
.m_msbzero
)
938 # *sigh* not entirely obvious: count leading zeros (clz)
939 # with a PriorityEncoder: to find from the MSB
940 # we reverse the order of the bits.
941 temp_m
= Signal(mwid
, reset_less
=True)
942 temp_s
= Signal(mwid
+1, reset_less
=True)
943 clz
= Signal((len(in_z
.e
), True), reset_less
=True)
945 # cat round and guard bits back into the mantissa
946 temp_m
.eq(Cat(in_of
.round_bit
, in_of
.guard
, in_z
.m
)),
947 pe
.i
.eq(temp_m
[::-1]), # inverted
948 clz
.eq(pe
.o
), # count zeros from MSB down
949 temp_s
.eq(temp_m
<< clz
), # shift mantissa UP
950 self
.out_z
.e
.eq(in_z
.e
- clz
), # DECREASE exponent
951 self
.out_z
.m
.eq(temp_s
[2:]), # exclude bits 0&1
957 class FPNorm1ModSingle
:
959 def __init__(self
, width
):
961 self
.out_norm
= Signal(reset_less
=True)
962 self
.in_z
= FPNumBase(width
, False)
963 self
.in_of
= Overflow()
964 self
.out_z
= FPNumBase(width
, False)
965 self
.out_of
= Overflow()
967 def setup(self
, m
, in_z
, in_of
, out_z
):
968 """ links module to inputs and outputs
970 m
.submodules
.normalise_1
= self
972 m
.d
.comb
+= self
.in_z
.eq(in_z
)
973 m
.d
.comb
+= self
.in_of
.eq(in_of
)
975 m
.d
.comb
+= out_z
.eq(self
.out_z
)
977 def elaborate(self
, platform
):
980 mwid
= self
.out_z
.m_width
+2
981 pe
= PriorityEncoder(mwid
)
982 m
.submodules
.norm_pe
= pe
984 m
.submodules
.norm1_out_z
= self
.out_z
985 m
.submodules
.norm1_out_overflow
= self
.out_of
986 m
.submodules
.norm1_in_z
= self
.in_z
987 m
.submodules
.norm1_in_overflow
= self
.in_of
989 in_z
= FPNumBase(self
.width
, False)
991 m
.submodules
.norm1_insel_z
= in_z
992 m
.submodules
.norm1_insel_overflow
= in_of
994 espec
= (len(in_z
.e
), True)
995 ediff_n126
= Signal(espec
, reset_less
=True)
996 msr
= MultiShiftRMerge(mwid
, espec
)
997 m
.submodules
.multishift_r
= msr
999 m
.d
.comb
+= in_z
.eq(self
.in_z
)
1000 m
.d
.comb
+= in_of
.eq(self
.in_of
)
1001 # initialise out from in (overridden below)
1002 m
.d
.comb
+= self
.out_z
.eq(in_z
)
1003 m
.d
.comb
+= self
.out_of
.eq(in_of
)
1004 # normalisation increase/decrease conditions
1005 decrease
= Signal(reset_less
=True)
1006 increase
= Signal(reset_less
=True)
1007 m
.d
.comb
+= decrease
.eq(in_z
.m_msbzero
& in_z
.exp_gt_n126
)
1008 m
.d
.comb
+= increase
.eq(in_z
.exp_lt_n126
)
1010 with m
.If(decrease
):
1011 # *sigh* not entirely obvious: count leading zeros (clz)
1012 # with a PriorityEncoder: to find from the MSB
1013 # we reverse the order of the bits.
1014 temp_m
= Signal(mwid
, reset_less
=True)
1015 temp_s
= Signal(mwid
+1, reset_less
=True)
1016 clz
= Signal((len(in_z
.e
), True), reset_less
=True)
1017 # make sure that the amount to decrease by does NOT
1018 # go below the minimum non-INF/NaN exponent
1019 limclz
= Mux(in_z
.exp_sub_n126
> pe
.o
, pe
.o
,
1022 # cat round and guard bits back into the mantissa
1023 temp_m
.eq(Cat(in_of
.round_bit
, in_of
.guard
, in_z
.m
)),
1024 pe
.i
.eq(temp_m
[::-1]), # inverted
1025 clz
.eq(limclz
), # count zeros from MSB down
1026 temp_s
.eq(temp_m
<< clz
), # shift mantissa UP
1027 self
.out_z
.e
.eq(in_z
.e
- clz
), # DECREASE exponent
1028 self
.out_z
.m
.eq(temp_s
[2:]), # exclude bits 0&1
1029 self
.out_of
.m0
.eq(temp_s
[2]), # copy of mantissa[0]
1030 # overflow in bits 0..1: got shifted too (leave sticky)
1031 self
.out_of
.guard
.eq(temp_s
[1]), # guard
1032 self
.out_of
.round_bit
.eq(temp_s
[0]), # round
1035 with m
.Elif(increase
):
1036 temp_m
= Signal(mwid
+1, reset_less
=True)
1038 temp_m
.eq(Cat(in_of
.sticky
, in_of
.round_bit
, in_of
.guard
,
1040 ediff_n126
.eq(in_z
.N126
- in_z
.e
),
1041 # connect multi-shifter to inp/out mantissa (and ediff)
1043 msr
.diff
.eq(ediff_n126
),
1044 self
.out_z
.m
.eq(msr
.m
[3:]),
1045 self
.out_of
.m0
.eq(temp_s
[3]), # copy of mantissa[0]
1046 # overflow in bits 0..1: got shifted too (leave sticky)
1047 self
.out_of
.guard
.eq(temp_s
[2]), # guard
1048 self
.out_of
.round_bit
.eq(temp_s
[1]), # round
1049 self
.out_of
.sticky
.eq(temp_s
[0]), # sticky
1050 self
.out_z
.e
.eq(in_z
.e
+ ediff_n126
),
1056 class FPNorm1ModMulti
:
1058 def __init__(self
, width
, single_cycle
=True):
1060 self
.in_select
= Signal(reset_less
=True)
1061 self
.out_norm
= Signal(reset_less
=True)
1062 self
.in_z
= FPNumBase(width
, False)
1063 self
.in_of
= Overflow()
1064 self
.temp_z
= FPNumBase(width
, False)
1065 self
.temp_of
= Overflow()
1066 self
.out_z
= FPNumBase(width
, False)
1067 self
.out_of
= Overflow()
1069 def elaborate(self
, platform
):
1072 m
.submodules
.norm1_out_z
= self
.out_z
1073 m
.submodules
.norm1_out_overflow
= self
.out_of
1074 m
.submodules
.norm1_temp_z
= self
.temp_z
1075 m
.submodules
.norm1_temp_of
= self
.temp_of
1076 m
.submodules
.norm1_in_z
= self
.in_z
1077 m
.submodules
.norm1_in_overflow
= self
.in_of
1079 in_z
= FPNumBase(self
.width
, False)
1081 m
.submodules
.norm1_insel_z
= in_z
1082 m
.submodules
.norm1_insel_overflow
= in_of
1084 # select which of temp or in z/of to use
1085 with m
.If(self
.in_select
):
1086 m
.d
.comb
+= in_z
.eq(self
.in_z
)
1087 m
.d
.comb
+= in_of
.eq(self
.in_of
)
1089 m
.d
.comb
+= in_z
.eq(self
.temp_z
)
1090 m
.d
.comb
+= in_of
.eq(self
.temp_of
)
1091 # initialise out from in (overridden below)
1092 m
.d
.comb
+= self
.out_z
.eq(in_z
)
1093 m
.d
.comb
+= self
.out_of
.eq(in_of
)
1094 # normalisation increase/decrease conditions
1095 decrease
= Signal(reset_less
=True)
1096 increase
= Signal(reset_less
=True)
1097 m
.d
.comb
+= decrease
.eq(in_z
.m_msbzero
& in_z
.exp_gt_n126
)
1098 m
.d
.comb
+= increase
.eq(in_z
.exp_lt_n126
)
1099 m
.d
.comb
+= self
.out_norm
.eq(decrease | increase
) # loop-end
1101 with m
.If(decrease
):
1103 self
.out_z
.e
.eq(in_z
.e
- 1), # DECREASE exponent
1104 self
.out_z
.m
.eq(in_z
.m
<< 1), # shift mantissa UP
1105 self
.out_z
.m
[0].eq(in_of
.guard
), # steal guard (was tot[2])
1106 self
.out_of
.guard
.eq(in_of
.round_bit
), # round (was tot[1])
1107 self
.out_of
.round_bit
.eq(0), # reset round bit
1108 self
.out_of
.m0
.eq(in_of
.guard
),
1111 with m
.Elif(increase
):
1113 self
.out_z
.e
.eq(in_z
.e
+ 1), # INCREASE exponent
1114 self
.out_z
.m
.eq(in_z
.m
>> 1), # shift mantissa DOWN
1115 self
.out_of
.guard
.eq(in_z
.m
[0]),
1116 self
.out_of
.m0
.eq(in_z
.m
[1]),
1117 self
.out_of
.round_bit
.eq(in_of
.guard
),
1118 self
.out_of
.sticky
.eq(in_of
.sticky | in_of
.round_bit
)
1124 class FPNorm1Single(FPState
, FPID
):
1126 def __init__(self
, width
, id_wid
, single_cycle
=True):
1127 FPID
.__init
__(self
, id_wid
)
1128 FPState
.__init
__(self
, "normalise_1")
1129 self
.mod
= FPNorm1ModSingle(width
)
1130 self
.out_norm
= Signal(reset_less
=True)
1131 self
.out_z
= FPNumBase(width
)
1132 self
.out_roundz
= Signal(reset_less
=True)
1134 def setup(self
, m
, in_z
, in_of
, in_mid
):
1135 """ links module to inputs and outputs
1137 self
.mod
.setup(m
, in_z
, in_of
, self
.out_z
)
1139 if self
.in_mid
is not None:
1140 m
.d
.comb
+= self
.in_mid
.eq(in_mid
)
1142 def action(self
, m
):
1144 m
.d
.sync
+= self
.out_roundz
.eq(self
.mod
.out_of
.roundz
)
1148 class FPNorm1Multi(FPState
, FPID
):
1150 def __init__(self
, width
, id_wid
):
1151 FPID
.__init
__(self
, id_wid
)
1152 FPState
.__init
__(self
, "normalise_1")
1153 self
.mod
= FPNorm1ModMulti(width
)
1154 self
.stb
= Signal(reset_less
=True)
1155 self
.ack
= Signal(reset
=0, reset_less
=True)
1156 self
.out_norm
= Signal(reset_less
=True)
1157 self
.in_accept
= Signal(reset_less
=True)
1158 self
.temp_z
= FPNumBase(width
)
1159 self
.temp_of
= Overflow()
1160 self
.out_z
= FPNumBase(width
)
1161 self
.out_roundz
= Signal(reset_less
=True)
1163 def setup(self
, m
, in_z
, in_of
, norm_stb
, in_mid
):
1164 """ links module to inputs and outputs
1166 self
.mod
.setup(m
, in_z
, in_of
, norm_stb
,
1167 self
.in_accept
, self
.temp_z
, self
.temp_of
,
1168 self
.out_z
, self
.out_norm
)
1170 m
.d
.comb
+= self
.stb
.eq(norm_stb
)
1171 m
.d
.sync
+= self
.ack
.eq(0) # sets to zero when not in normalise_1 state
1173 if self
.in_mid
is not None:
1174 m
.d
.comb
+= self
.in_mid
.eq(in_mid
)
1176 def action(self
, m
):
1178 m
.d
.comb
+= self
.in_accept
.eq((~self
.ack
) & (self
.stb
))
1179 m
.d
.sync
+= self
.temp_of
.eq(self
.mod
.out_of
)
1180 m
.d
.sync
+= self
.temp_z
.eq(self
.out_z
)
1181 with m
.If(self
.out_norm
):
1182 with m
.If(self
.in_accept
):
1187 m
.d
.sync
+= self
.ack
.eq(0)
1189 # normalisation not required (or done).
1191 m
.d
.sync
+= self
.ack
.eq(1)
1192 m
.d
.sync
+= self
.out_roundz
.eq(self
.mod
.out_of
.roundz
)
1195 class FPNormToPack(FPState
, FPID
):
1197 def __init__(self
, width
, id_wid
):
1198 FPID
.__init
__(self
, id_wid
)
1199 FPState
.__init
__(self
, "normalise_1")
1202 def setup(self
, m
, in_z
, in_of
, in_mid
):
1203 """ links module to inputs and outputs
1206 # Normalisation (chained to input in_z+in_of)
1207 nmod
= FPNorm1ModSingle(self
.width
)
1208 n_out_z
= FPNumBase(self
.width
)
1209 n_out_roundz
= Signal(reset_less
=True)
1210 nmod
.setup(m
, in_z
, in_of
, n_out_z
)
1212 # Rounding (chained to normalisation)
1213 rmod
= FPRoundMod(self
.width
)
1214 r_out_z
= FPNumBase(self
.width
)
1215 rmod
.setup(m
, n_out_z
, n_out_roundz
)
1216 m
.d
.comb
+= n_out_roundz
.eq(nmod
.out_of
.roundz
)
1217 m
.d
.comb
+= r_out_z
.eq(rmod
.out_z
)
1219 # Corrections (chained to rounding)
1220 cmod
= FPCorrectionsMod(self
.width
)
1221 c_out_z
= FPNumBase(self
.width
)
1222 cmod
.setup(m
, r_out_z
)
1223 m
.d
.comb
+= c_out_z
.eq(cmod
.out_z
)
1225 # Pack (chained to corrections)
1226 self
.pmod
= FPPackMod(self
.width
)
1227 self
.out_z
= FPNumBase(self
.width
)
1228 self
.pmod
.setup(m
, c_out_z
)
1231 if self
.in_mid
is not None:
1232 m
.d
.comb
+= self
.in_mid
.eq(in_mid
)
1234 def action(self
, m
):
1235 self
.idsync(m
) # copies incoming ID to outgoing
1236 m
.d
.sync
+= self
.out_z
.v
.eq(self
.pmod
.out_z
.v
) # outputs packed result
1237 m
.next
= "pack_put_z"
1242 def __init__(self
, width
):
1243 self
.in_roundz
= Signal(reset_less
=True)
1244 self
.in_z
= FPNumBase(width
, False)
1245 self
.out_z
= FPNumBase(width
, False)
1247 def setup(self
, m
, in_z
, roundz
):
1248 m
.submodules
.roundz
= self
1250 m
.d
.comb
+= self
.in_z
.eq(in_z
)
1251 m
.d
.comb
+= self
.in_roundz
.eq(roundz
)
1253 def elaborate(self
, platform
):
1255 m
.d
.comb
+= self
.out_z
.eq(self
.in_z
)
1256 with m
.If(self
.in_roundz
):
1257 m
.d
.comb
+= self
.out_z
.m
.eq(self
.in_z
.m
+ 1) # mantissa rounds up
1258 with m
.If(self
.in_z
.m
== self
.in_z
.m1s
): # all 1s
1259 m
.d
.comb
+= self
.out_z
.e
.eq(self
.in_z
.e
+ 1) # exponent up
1263 class FPRound(FPState
, FPID
):
1265 def __init__(self
, width
, id_wid
):
1266 FPState
.__init
__(self
, "round")
1267 FPID
.__init
__(self
, id_wid
)
1268 self
.mod
= FPRoundMod(width
)
1269 self
.out_z
= FPNumBase(width
)
1271 def setup(self
, m
, in_z
, roundz
, in_mid
):
1272 """ links module to inputs and outputs
1274 self
.mod
.setup(m
, in_z
, roundz
)
1276 if self
.in_mid
is not None:
1277 m
.d
.comb
+= self
.in_mid
.eq(in_mid
)
1279 def action(self
, m
):
1281 m
.d
.sync
+= self
.out_z
.eq(self
.mod
.out_z
)
1282 m
.next
= "corrections"
1285 class FPCorrectionsMod
:
1287 def __init__(self
, width
):
1288 self
.in_z
= FPNumOut(width
, False)
1289 self
.out_z
= FPNumOut(width
, False)
1291 def setup(self
, m
, in_z
):
1292 """ links module to inputs and outputs
1294 m
.submodules
.corrections
= self
1295 m
.d
.comb
+= self
.in_z
.eq(in_z
)
1297 def elaborate(self
, platform
):
1299 m
.submodules
.corr_in_z
= self
.in_z
1300 m
.submodules
.corr_out_z
= self
.out_z
1301 m
.d
.comb
+= self
.out_z
.eq(self
.in_z
)
1302 with m
.If(self
.in_z
.is_denormalised
):
1303 m
.d
.comb
+= self
.out_z
.e
.eq(self
.in_z
.N127
)
1307 class FPCorrections(FPState
, FPID
):
1309 def __init__(self
, width
, id_wid
):
1310 FPState
.__init
__(self
, "corrections")
1311 FPID
.__init
__(self
, id_wid
)
1312 self
.mod
= FPCorrectionsMod(width
)
1313 self
.out_z
= FPNumBase(width
)
1315 def setup(self
, m
, in_z
, in_mid
):
1316 """ links module to inputs and outputs
1318 self
.mod
.setup(m
, in_z
)
1319 if self
.in_mid
is not None:
1320 m
.d
.comb
+= self
.in_mid
.eq(in_mid
)
1322 def action(self
, m
):
1324 m
.d
.sync
+= self
.out_z
.eq(self
.mod
.out_z
)
1330 def __init__(self
, width
):
1331 self
.in_z
= FPNumOut(width
, False)
1332 self
.out_z
= FPNumOut(width
, False)
1334 def setup(self
, m
, in_z
):
1335 """ links module to inputs and outputs
1337 m
.submodules
.pack
= self
1338 m
.d
.comb
+= self
.in_z
.eq(in_z
)
1340 def elaborate(self
, platform
):
1342 m
.submodules
.pack_in_z
= self
.in_z
1343 with m
.If(self
.in_z
.is_overflowed
):
1344 m
.d
.comb
+= self
.out_z
.inf(self
.in_z
.s
)
1346 m
.d
.comb
+= self
.out_z
.create(self
.in_z
.s
, self
.in_z
.e
, self
.in_z
.m
)
1350 class FPPack(FPState
, FPID
):
1352 def __init__(self
, width
, id_wid
):
1353 FPState
.__init
__(self
, "pack")
1354 FPID
.__init
__(self
, id_wid
)
1355 self
.mod
= FPPackMod(width
)
1356 self
.out_z
= FPNumOut(width
, False)
1358 def setup(self
, m
, in_z
, in_mid
):
1359 """ links module to inputs and outputs
1361 self
.mod
.setup(m
, in_z
)
1362 if self
.in_mid
is not None:
1363 m
.d
.comb
+= self
.in_mid
.eq(in_mid
)
1365 def action(self
, m
):
1367 m
.d
.sync
+= self
.out_z
.v
.eq(self
.mod
.out_z
.v
)
1368 m
.next
= "pack_put_z"
1371 class FPPutZ(FPState
):
1373 def __init__(self
, state
, in_z
, out_z
, in_mid
, out_mid
, to_state
=None):
1374 FPState
.__init
__(self
, state
)
1375 if to_state
is None:
1376 to_state
= "get_ops"
1377 self
.to_state
= to_state
1380 self
.in_mid
= in_mid
1381 self
.out_mid
= out_mid
1383 def action(self
, m
):
1384 if self
.in_mid
is not None:
1385 m
.d
.sync
+= self
.out_mid
.eq(self
.in_mid
)
1387 self
.out_z
.v
.eq(self
.in_z
.v
)
1389 with m
.If(self
.out_z
.stb
& self
.out_z
.ack
):
1390 m
.d
.sync
+= self
.out_z
.stb
.eq(0)
1391 m
.next
= self
.to_state
1393 m
.d
.sync
+= self
.out_z
.stb
.eq(1)
1396 class FPPutZIdx(FPState
):
1398 def __init__(self
, state
, in_z
, out_zs
, in_mid
, to_state
=None):
1399 FPState
.__init
__(self
, state
)
1400 if to_state
is None:
1401 to_state
= "get_ops"
1402 self
.to_state
= to_state
1404 self
.out_zs
= out_zs
1405 self
.in_mid
= in_mid
1407 def action(self
, m
):
1408 outz_stb
= Signal(reset_less
=True)
1409 outz_ack
= Signal(reset_less
=True)
1410 m
.d
.comb
+= [outz_stb
.eq(self
.out_zs
[self
.in_mid
].stb
),
1411 outz_ack
.eq(self
.out_zs
[self
.in_mid
].ack
),
1414 self
.out_zs
[self
.in_mid
].v
.eq(self
.in_z
.v
)
1416 with m
.If(outz_stb
& outz_ack
):
1417 m
.d
.sync
+= self
.out_zs
[self
.in_mid
].stb
.eq(0)
1418 m
.next
= self
.to_state
1420 m
.d
.sync
+= self
.out_zs
[self
.in_mid
].stb
.eq(1)
1423 class FPADDBaseMod(FPID
):
1425 def __init__(self
, width
, id_wid
=None, single_cycle
=False, compact
=True):
1428 * width: bit-width of IEEE754. supported: 16, 32, 64
1429 * id_wid: an identifier that is sync-connected to the input
1430 * single_cycle: True indicates each stage to complete in 1 clock
1431 * compact: True indicates a reduced number of stages
1433 FPID
.__init
__(self
, id_wid
)
1435 self
.single_cycle
= single_cycle
1436 self
.compact
= compact
1438 self
.in_t
= Trigger()
1439 self
.in_a
= Signal(width
)
1440 self
.in_b
= Signal(width
)
1441 self
.out_z
= FPOp(width
)
1445 def add_state(self
, state
):
1446 self
.states
.append(state
)
1449 def get_fragment(self
, platform
=None):
1450 """ creates the HDL code-fragment for FPAdd
1453 m
.submodules
.out_z
= self
.out_z
1454 m
.submodules
.in_t
= self
.in_t
1456 self
.get_compact_fragment(m
, platform
)
1458 self
.get_longer_fragment(m
, platform
)
1460 with m
.FSM() as fsm
:
1462 for state
in self
.states
:
1463 with m
.State(state
.state_from
):
1468 def get_longer_fragment(self
, m
, platform
=None):
1470 get
= self
.add_state(FPGet2Op("get_ops", "special_cases",
1471 self
.in_a
, self
.in_b
, self
.width
))
1472 get
.setup(m
, self
.in_a
, self
.in_b
, self
.in_t
.stb
, self
.in_t
.ack
)
1476 sc
= self
.add_state(FPAddSpecialCases(self
.width
, self
.id_wid
))
1477 sc
.setup(m
, a
, b
, self
.in_mid
)
1479 dn
= self
.add_state(FPAddDeNorm(self
.width
, self
.id_wid
))
1480 dn
.setup(m
, a
, b
, sc
.in_mid
)
1482 if self
.single_cycle
:
1483 alm
= self
.add_state(FPAddAlignSingle(self
.width
, self
.id_wid
))
1484 alm
.setup(m
, dn
.out_a
, dn
.out_b
, dn
.in_mid
)
1486 alm
= self
.add_state(FPAddAlignMulti(self
.width
, self
.id_wid
))
1487 alm
.setup(m
, dn
.out_a
, dn
.out_b
, dn
.in_mid
)
1489 add0
= self
.add_state(FPAddStage0(self
.width
, self
.id_wid
))
1490 add0
.setup(m
, alm
.out_a
, alm
.out_b
, alm
.in_mid
)
1492 add1
= self
.add_state(FPAddStage1(self
.width
, self
.id_wid
))
1493 add1
.setup(m
, add0
.out_tot
, add0
.out_z
, add0
.in_mid
)
1495 if self
.single_cycle
:
1496 n1
= self
.add_state(FPNorm1Single(self
.width
, self
.id_wid
))
1497 n1
.setup(m
, add1
.out_z
, add1
.out_of
, add0
.in_mid
)
1499 n1
= self
.add_state(FPNorm1Multi(self
.width
, self
.id_wid
))
1500 n1
.setup(m
, add1
.out_z
, add1
.out_of
, add1
.norm_stb
, add0
.in_mid
)
1502 rn
= self
.add_state(FPRound(self
.width
, self
.id_wid
))
1503 rn
.setup(m
, n1
.out_z
, n1
.out_roundz
, n1
.in_mid
)
1505 cor
= self
.add_state(FPCorrections(self
.width
, self
.id_wid
))
1506 cor
.setup(m
, rn
.out_z
, rn
.in_mid
)
1508 pa
= self
.add_state(FPPack(self
.width
, self
.id_wid
))
1509 pa
.setup(m
, cor
.out_z
, rn
.in_mid
)
1511 ppz
= self
.add_state(FPPutZ("pack_put_z", pa
.out_z
, self
.out_z
,
1512 pa
.in_mid
, self
.out_mid
))
1514 pz
= self
.add_state(FPPutZ("put_z", sc
.out_z
, self
.out_z
,
1515 pa
.in_mid
, self
.out_mid
))
1517 def get_compact_fragment(self
, m
, platform
=None):
1519 get
= self
.add_state(FPGet2Op("get_ops", "special_cases",
1520 self
.in_a
, self
.in_b
, self
.width
))
1521 get
.setup(m
, self
.in_a
, self
.in_b
, self
.in_t
.stb
, self
.in_t
.ack
)
1525 sc
= self
.add_state(FPAddSpecialCasesDeNorm(self
.width
, self
.id_wid
))
1526 sc
.setup(m
, a
, b
, self
.in_mid
)
1528 alm
= self
.add_state(FPAddAlignSingleAdd(self
.width
, self
.id_wid
))
1529 alm
.setup(m
, sc
.out_a
, sc
.out_b
, sc
.in_mid
)
1531 n1
= self
.add_state(FPNormToPack(self
.width
, self
.id_wid
))
1532 n1
.setup(m
, alm
.out_z
, alm
.out_of
, alm
.in_mid
)
1534 ppz
= self
.add_state(FPPutZ("pack_put_z", n1
.out_z
, self
.out_z
,
1535 n1
.in_mid
, self
.out_mid
))
1537 pz
= self
.add_state(FPPutZ("put_z", sc
.out_z
, self
.out_z
,
1538 sc
.in_mid
, self
.out_mid
))
1541 class FPADDBase(FPState
, FPID
):
1543 def __init__(self
, width
, id_wid
=None, single_cycle
=False):
1546 * width: bit-width of IEEE754. supported: 16, 32, 64
1547 * id_wid: an identifier that is sync-connected to the input
1548 * single_cycle: True indicates each stage to complete in 1 clock
1550 FPID
.__init
__(self
, id_wid
)
1551 FPState
.__init
__(self
, "fpadd")
1553 self
.single_cycle
= single_cycle
1554 self
.mod
= FPADDBaseMod(width
, id_wid
, single_cycle
)
1556 self
.in_t
= Trigger()
1557 self
.in_a
= Signal(width
)
1558 self
.in_b
= Signal(width
)
1559 #self.out_z = FPOp(width)
1561 self
.z_done
= Signal(reset_less
=True) # connects to out_z Strobe
1562 self
.in_accept
= Signal(reset_less
=True)
1563 self
.add_stb
= Signal(reset_less
=True)
1564 self
.add_ack
= Signal(reset
=0, reset_less
=True)
1566 def setup(self
, m
, a
, b
, add_stb
, in_mid
, out_z
, out_mid
):
1568 self
.out_mid
= out_mid
1569 m
.d
.comb
+= [self
.in_a
.eq(a
),
1571 self
.mod
.in_a
.eq(self
.in_a
),
1572 self
.mod
.in_b
.eq(self
.in_b
),
1573 self
.in_mid
.eq(in_mid
),
1574 self
.mod
.in_mid
.eq(self
.in_mid
),
1575 self
.z_done
.eq(self
.mod
.out_z
.trigger
),
1576 #self.add_stb.eq(add_stb),
1577 self
.mod
.in_t
.stb
.eq(self
.in_t
.stb
),
1578 self
.in_t
.ack
.eq(self
.mod
.in_t
.ack
),
1579 self
.out_mid
.eq(self
.mod
.out_mid
),
1580 self
.out_z
.v
.eq(self
.mod
.out_z
.v
),
1581 self
.out_z
.stb
.eq(self
.mod
.out_z
.stb
),
1582 self
.mod
.out_z
.ack
.eq(self
.out_z
.ack
),
1585 m
.d
.sync
+= self
.add_stb
.eq(add_stb
)
1586 m
.d
.sync
+= self
.add_ack
.eq(0) # sets to zero when not in active state
1587 m
.d
.sync
+= self
.out_z
.ack
.eq(0) # likewise
1588 #m.d.sync += self.in_t.stb.eq(0)
1590 m
.submodules
.fpadd
= self
.mod
1592 def action(self
, m
):
1594 # in_accept is set on incoming strobe HIGH and ack LOW.
1595 m
.d
.comb
+= self
.in_accept
.eq((~self
.add_ack
) & (self
.add_stb
))
1597 #with m.If(self.in_t.ack):
1598 # m.d.sync += self.in_t.stb.eq(0)
1599 with m
.If(~self
.z_done
):
1600 # not done: test for accepting an incoming operand pair
1601 with m
.If(self
.in_accept
):
1603 self
.add_ack
.eq(1), # acknowledge receipt...
1604 self
.in_t
.stb
.eq(1), # initiate add
1607 m
.d
.sync
+= [self
.add_ack
.eq(0),
1608 self
.in_t
.stb
.eq(0),
1609 self
.out_z
.ack
.eq(1),
1612 # done: acknowledge, and write out id and value
1613 m
.d
.sync
+= [self
.add_ack
.eq(1),
1620 if self
.in_mid
is not None:
1621 m
.d
.sync
+= self
.out_mid
.eq(self
.mod
.out_mid
)
1624 self
.out_z
.v
.eq(self
.mod
.out_z
.v
)
1626 # move to output state on detecting z ack
1627 with m
.If(self
.out_z
.trigger
):
1628 m
.d
.sync
+= self
.out_z
.stb
.eq(0)
1631 m
.d
.sync
+= self
.out_z
.stb
.eq(1)
1634 def __init__(self
, width
, id_wid
):
1636 self
.id_wid
= id_wid
1638 for i
in range(rs_sz
):
1640 out_z
.name
= "out_z_%d" % i
1642 self
.res
= Array(res
)
1643 self
.in_z
= FPOp(width
)
1644 self
.in_mid
= Signal(self
.id_wid
, reset_less
=True)
1646 def setup(self
, m
, in_z
, in_mid
):
1647 m
.d
.comb
+= [self
.in_z
.eq(in_z
),
1648 self
.in_mid
.eq(in_mid
)]
1650 def get_fragment(self
, platform
=None):
1651 """ creates the HDL code-fragment for FPAdd
1654 m
.submodules
.res_in_z
= self
.in_z
1655 m
.submodules
+= self
.res
1667 """ FPADD: stages as follows:
1673 FPAddBase---> FPAddBaseMod
1675 PutZ GetOps->Specials->Align->Add1/2->Norm->Round/Pack->PutZ
1677 FPAddBase is tricky: it is both a stage and *has* stages.
1678 Connection to FPAddBaseMod therefore requires an in stb/ack
1679 and an out stb/ack. Just as with Add1-Norm1 interaction, FPGetOp
1680 needs to be the thing that raises the incoming stb.
1683 def __init__(self
, width
, id_wid
=None, single_cycle
=False, rs_sz
=2):
1686 * width: bit-width of IEEE754. supported: 16, 32, 64
1687 * id_wid: an identifier that is sync-connected to the input
1688 * single_cycle: True indicates each stage to complete in 1 clock
1691 self
.id_wid
= id_wid
1692 self
.single_cycle
= single_cycle
1694 #self.out_z = FPOp(width)
1695 self
.ids
= FPID(id_wid
)
1698 for i
in range(rs_sz
):
1701 in_a
.name
= "in_a_%d" % i
1702 in_b
.name
= "in_b_%d" % i
1703 rs
.append((in_a
, in_b
))
1707 for i
in range(rs_sz
):
1709 out_z
.name
= "out_z_%d" % i
1711 self
.res
= Array(res
)
1715 def add_state(self
, state
):
1716 self
.states
.append(state
)
1719 def get_fragment(self
, platform
=None):
1720 """ creates the HDL code-fragment for FPAdd
1723 m
.submodules
+= self
.rs
1725 in_a
= self
.rs
[0][0]
1726 in_b
= self
.rs
[0][1]
1728 out_z
= FPOp(self
.width
)
1729 out_mid
= Signal(self
.id_wid
, reset_less
=True)
1730 m
.submodules
.out_z
= out_z
1732 geta
= self
.add_state(FPGetOp("get_a", "get_b",
1737 getb
= self
.add_state(FPGetOp("get_b", "fpadd",
1742 ab
= FPADDBase(self
.width
, self
.id_wid
, self
.single_cycle
)
1743 ab
= self
.add_state(ab
)
1744 ab
.setup(m
, a
, b
, getb
.out_decode
, self
.ids
.in_mid
,
1747 pz
= self
.add_state(FPPutZIdx("put_z", ab
.out_z
, self
.res
,
1750 with m
.FSM() as fsm
:
1752 for state
in self
.states
:
1753 with m
.State(state
.state_from
):
1759 if __name__
== "__main__":
1761 alu
= FPADD(width
=32, id_wid
=5, single_cycle
=True)
1762 main(alu
, ports
=alu
.rs
[0][0].ports() + \
1763 alu
.rs
[0][1].ports() + \
1764 alu
.res
[0].ports() + \
1765 [alu
.ids
.in_mid
, alu
.ids
.out_mid
])
1767 alu
= FPADDBase(width
=32, id_wid
=5, single_cycle
=True)
1768 main(alu
, ports
=[alu
.in_a
, alu
.in_b
] + \
1769 alu
.in_t
.ports() + \
1770 alu
.out_z
.ports() + \
1771 [alu
.in_mid
, alu
.out_mid
])
1774 # works... but don't use, just do "python fname.py convert -t v"
1775 #print (verilog.convert(alu, ports=[
1776 # ports=alu.in_a.ports() + \
1777 # alu.in_b.ports() + \
1778 # alu.out_z.ports())