011019fcfd1feafabccc2eb01d84f0538e0b0e3c
1 """ Pipeline and BufferedHandshake implementation, conforming to the same API.
2 For multi-input and multi-output variants, see multipipe.
4 Associated development bugs:
5 * http://bugs.libre-riscv.org/show_bug.cgi?id=64
6 * http://bugs.libre-riscv.org/show_bug.cgi?id=57
11 a strategically very important function that is identical in function
12 to nmigen's Signal.eq function, except it may take objects, or a list
13 of objects, or a tuple of objects, and where objects may also be
19 stage requires compliance with a strict API that may be
20 implemented in several means, including as a static class.
21 the methods of a stage instance must be as follows:
23 * ispec() - Input data format specification
24 returns an object or a list or tuple of objects, or
25 a Record, each object having an "eq" function which
26 takes responsibility for copying by assignment all
28 * ospec() - Output data format specification
29 requirements as for ospec
30 * process(m, i) - Processes an ispec-formatted object
31 returns a combinatorial block of a result that
32 may be assigned to the output, by way of the "eq"
34 * setup(m, i) - Optional function for setting up submodules
35 may be used for more complex stages, to link
36 the input (i) to submodules. must take responsibility
37 for adding those submodules to the module (m).
38 the submodules must be combinatorial blocks and
39 must have their inputs and output linked combinatorially.
41 Both StageCls (for use with non-static classes) and Stage (for use
42 by static classes) are abstract classes from which, for convenience
43 and as a courtesy to other developers, anything conforming to the
44 Stage API may *choose* to derive.
49 A useful combinatorial wrapper around stages that chains them together
50 and then presents a Stage-API-conformant interface. By presenting
51 the same API as the stages it wraps, it can clearly be used recursively.
56 A convenience class that takes an input shape, output shape, a
57 "processing" function and an optional "setup" function. Honestly
58 though, there's not much more effort to just... create a class
59 that returns a couple of Records (see ExampleAddRecordStage in
65 A convenience class that takes a single function as a parameter,
66 that is chain-called to create the exact same input and output spec.
67 It has a process() function that simply returns its input.
69 Instances of this class are completely redundant if handed to
70 StageChain, however when passed to UnbufferedPipeline they
71 can be used to introduce a single clock delay.
76 The base class for pipelines. Contains previous and next ready/valid/data.
77 Also has an extremely useful "connect" function that can be used to
78 connect a chain of pipelines and present the exact same prev/next
84 A simple stalling clock-synchronised pipeline that has no buffering
85 (unlike BufferedHandshake). Data flows on *every* clock cycle when
86 the conditions are right (this is nominally when the input is valid
87 and the output is ready).
89 A stall anywhere along the line will result in a stall back-propagating
90 down the entire chain. The BufferedHandshake by contrast will buffer
91 incoming data, allowing previous stages one clock cycle's grace before
94 An advantage of the UnbufferedPipeline over the Buffered one is
95 that the amount of logic needed (number of gates) is greatly
96 reduced (no second set of buffers basically)
98 The disadvantage of the UnbufferedPipeline is that the valid/ready
99 logic, if chained together, is *combinatorial*, resulting in
100 progressively larger gate delay.
102 PassThroughHandshake:
105 A Control class that introduces a single clock delay, passing its
106 data through unaltered. Unlike RegisterPipeline (which relies
107 on UnbufferedPipeline and PassThroughStage) it handles ready/valid
113 A convenience class that, because UnbufferedPipeline introduces a single
114 clock delay, when its stage is a PassThroughStage, it results in a Pipeline
115 stage that, duh, delays its (unmodified) input by one clock cycle.
120 nmigen implementation of buffered pipeline stage, based on zipcpu:
121 https://zipcpu.com/blog/2017/08/14/strategies-for-pipelining.html
123 this module requires quite a bit of thought to understand how it works
124 (and why it is needed in the first place). reading the above is
125 *strongly* recommended.
127 unlike john dawson's IEEE754 FPU STB/ACK signalling, which requires
128 the STB / ACK signals to raise and lower (on separate clocks) before
129 data may proceeed (thus only allowing one piece of data to proceed
130 on *ALTERNATE* cycles), the signalling here is a true pipeline
131 where data will flow on *every* clock when the conditions are right.
133 input acceptance conditions are when:
134 * incoming previous-stage strobe (p.i_valid) is HIGH
135 * outgoing previous-stage ready (p.o_ready) is LOW
137 output transmission conditions are when:
138 * outgoing next-stage strobe (n.o_valid) is HIGH
139 * outgoing next-stage ready (n.i_ready) is LOW
141 the tricky bit is when the input has valid data and the output is not
142 ready to accept it. if it wasn't for the clock synchronisation, it
143 would be possible to tell the input "hey don't send that data, we're
144 not ready". unfortunately, it's not possible to "change the past":
145 the previous stage *has no choice* but to pass on its data.
147 therefore, the incoming data *must* be accepted - and stored: that
148 is the responsibility / contract that this stage *must* accept.
149 on the same clock, it's possible to tell the input that it must
150 not send any more data. this is the "stall" condition.
152 we now effectively have *two* possible pieces of data to "choose" from:
153 the buffered data, and the incoming data. the decision as to which
154 to process and output is based on whether we are in "stall" or not.
155 i.e. when the next stage is no longer ready, the output comes from
156 the buffer if a stall had previously occurred, otherwise it comes
157 direct from processing the input.
159 this allows us to respect a synchronous "travelling STB" with what
160 dan calls a "buffered handshake".
162 it's quite a complex state machine!
167 Synchronised pipeline, Based on:
168 https://github.com/ZipCPU/dbgbus/blob/master/hexbus/rtl/hbdeword.v
171 from nmigen
import Signal
, Cat
, Const
, Mux
, Module
, Value
172 from nmigen
.cli
import verilog
, rtlil
173 from nmigen
.lib
.fifo
import SyncFIFO
, SyncFIFOBuffered
174 from nmigen
.hdl
.ast
import ArrayProxy
175 from nmigen
.hdl
.rec
import Record
, Layout
177 from abc
import ABCMeta
, abstractmethod
178 from collections
.abc
import Sequence
179 from queue
import Queue
182 class RecordObject(Record
):
183 def __init__(self
, layout
=None, name
=None):
184 Record
.__init
__(self
, layout
=layout
or [], name
=None)
186 def __setattr__(self
, k
, v
):
187 if k
in dir(Record
) or "fields" not in self
.__dict
__:
188 return object.__setattr
__(self
, k
, v
)
190 if isinstance(v
, Record
):
191 newlayout
= {k
: (k
, v
.layout
)}
193 newlayout
= {k
: (k
, v
.shape())}
194 self
.layout
.fields
.update(newlayout
)
197 for x
in self
.fields
.values():
202 """ contains signals that come *from* the previous stage (both in and out)
203 * i_valid: previous stage indicating all incoming data is valid.
204 may be a multi-bit signal, where all bits are required
205 to be asserted to indicate "valid".
206 * o_ready: output to next stage indicating readiness to accept data
207 * i_data : an input - added by the user of this class
210 def __init__(self
, i_width
=1, stage_ctl
=False):
211 self
.stage_ctl
= stage_ctl
212 self
.i_valid
= Signal(i_width
, name
="p_i_valid") # prev >>in self
213 self
._o
_ready
= Signal(name
="p_o_ready") # prev <<out self
214 self
.i_data
= None # XXX MUST BE ADDED BY USER
216 self
.s_o_ready
= Signal(name
="p_s_o_rdy") # prev <<out self
220 """ public-facing API: indicates (externally) that stage is ready
223 return self
.s_o_ready
# set dynamically by stage
224 return self
._o
_ready
# return this when not under dynamic control
226 def _connect_in(self
, prev
, direct
=False, fn
=None):
227 """ internal helper function to connect stage to an input source.
228 do not use to connect stage-to-stage!
230 i_valid
= prev
.i_valid
if direct
else prev
.i_valid_test
231 i_data
= fn(prev
.i_data
) if fn
is not None else prev
.i_data
232 return [self
.i_valid
.eq(i_valid
),
233 prev
.o_ready
.eq(self
.o_ready
),
234 eq(self
.i_data
, i_data
),
238 def i_valid_test(self
):
239 vlen
= len(self
.i_valid
)
241 # multi-bit case: valid only when i_valid is all 1s
242 all1s
= Const(-1, (len(self
.i_valid
), False))
243 i_valid
= (self
.i_valid
== all1s
)
245 # single-bit i_valid case
246 i_valid
= self
.i_valid
248 # when stage indicates not ready, incoming data
249 # must "appear" to be not ready too
251 i_valid
= i_valid
& self
.s_o_ready
257 """ contains the signals that go *to* the next stage (both in and out)
258 * o_valid: output indicating to next stage that data is valid
259 * i_ready: input from next stage indicating that it can accept data
260 * o_data : an output - added by the user of this class
262 def __init__(self
, stage_ctl
=False):
263 self
.stage_ctl
= stage_ctl
264 self
.o_valid
= Signal(name
="n_o_valid") # self out>> next
265 self
.i_ready
= Signal(name
="n_i_ready") # self <<in next
266 self
.o_data
= None # XXX MUST BE ADDED BY USER
268 self
.d_valid
= Signal(reset
=1) # INTERNAL (data valid)
271 def i_ready_test(self
):
273 return self
.i_ready
& self
.d_valid
276 def connect_to_next(self
, nxt
):
277 """ helper function to connect to the next stage data/valid/ready.
278 data/valid is passed *TO* nxt, and ready comes *IN* from nxt.
279 use this when connecting stage-to-stage
281 return [nxt
.i_valid
.eq(self
.o_valid
),
282 self
.i_ready
.eq(nxt
.o_ready
),
283 eq(nxt
.i_data
, self
.o_data
),
286 def _connect_out(self
, nxt
, direct
=False, fn
=None):
287 """ internal helper function to connect stage to an output source.
288 do not use to connect stage-to-stage!
290 i_ready
= nxt
.i_ready
if direct
else nxt
.i_ready_test
291 o_data
= fn(nxt
.o_data
) if fn
is not None else nxt
.o_data
292 return [nxt
.o_valid
.eq(self
.o_valid
),
293 self
.i_ready
.eq(i_ready
),
294 eq(o_data
, self
.o_data
),
299 """ a helper class for iterating twin-argument compound data structures.
301 Record is a special (unusual, recursive) case, where the input may be
302 specified as a dictionary (which may contain further dictionaries,
303 recursively), where the field names of the dictionary must match
304 the Record's field spec. Alternatively, an object with the same
305 member names as the Record may be assigned: it does not have to
308 ArrayProxy is also special-cased, it's a bit messy: whilst ArrayProxy
309 has an eq function, the object being assigned to it (e.g. a python
310 object) might not. despite the *input* having an eq function,
311 that doesn't help us, because it's the *ArrayProxy* that's being
312 assigned to. so.... we cheat. use the ports() function of the
313 python object, enumerate them, find out the list of Signals that way,
316 def iterator2(self
, o
, i
):
317 if isinstance(o
, dict):
318 yield from self
.dict_iter2(o
, i
)
320 if not isinstance(o
, Sequence
):
322 for (ao
, ai
) in zip(o
, i
):
323 #print ("visit", fn, ao, ai)
324 if isinstance(ao
, Record
):
325 yield from self
.record_iter2(ao
, ai
)
326 elif isinstance(ao
, ArrayProxy
) and not isinstance(ai
, Value
):
327 yield from self
.arrayproxy_iter2(ao
, ai
)
331 def dict_iter2(self
, o
, i
):
332 for (k
, v
) in o
.items():
333 print ("d-iter", v
, i
[k
])
337 def record_iter2(self
, ao
, ai
):
338 for idx
, (field_name
, field_shape
, _
) in enumerate(ao
.layout
):
339 if isinstance(field_shape
, Layout
):
343 if hasattr(val
, field_name
): # check for attribute
344 val
= getattr(val
, field_name
)
346 val
= val
[field_name
] # dictionary-style specification
347 yield from self
.iterator2(ao
.fields
[field_name
], val
)
349 def arrayproxy_iter2(self
, ao
, ai
):
351 op
= getattr(ao
, p
.name
)
352 print ("arrayproxy - p", p
, p
.name
)
353 yield from self
.iterator2(op
, p
)
356 """ a helper class for iterating single-argument compound data structures.
359 def iterate(self
, i
):
360 """ iterate a compound structure recursively using yield
362 if not isinstance(i
, Sequence
):
365 print ("iterate", ai
)
366 if isinstance(ai
, Record
):
367 print ("record", list(ai
.layout
))
368 yield from self
.record_iter(ai
)
369 elif isinstance(ai
, ArrayProxy
) and not isinstance(ai
, Value
):
370 yield from self
.array_iter(ai
)
374 def record_iter(self
, ai
):
375 for idx
, (field_name
, field_shape
, _
) in enumerate(ai
.layout
):
376 if isinstance(field_shape
, Layout
):
380 if hasattr(val
, field_name
): # check for attribute
381 val
= getattr(val
, field_name
)
383 val
= val
[field_name
] # dictionary-style specification
384 print ("recidx", idx
, field_name
, field_shape
, val
)
385 yield from self
.iterate(val
)
387 def array_iter(self
, ai
):
389 yield from self
.iterate(p
)
393 """ makes signals equal: a helper routine which identifies if it is being
394 passed a list (or tuple) of objects, or signals, or Records, and calls
395 the objects' eq function.
398 for (ao
, ai
) in Visitor2().iterator2(o
, i
):
400 if not isinstance(rres
, Sequence
):
408 """ flattens a compound structure recursively using Cat
410 NOTE: this does NOT work:
411 from nmigen.tools import flatten
412 res = list(flatten(i))
414 the reason is that flatten is not sophisticated enough,
415 and does not support iteration on Record:
417 File "nmigen/tools.py", line 12, in flatten
419 File "nmigen/hdl/rec.py", line 98, in __getitem__
420 .format(reference, name, ", ".join(self.fields))) from None
421 NameError: Unnamed record does not have a field '0'.
422 Did you mean one of: sig1, r2, r3?
424 #from nmigen.tools import flatten
425 #res = list(flatten(i))
426 res
= list(Visitor().iterate(i
))
430 class StageCls(metaclass
=ABCMeta
):
431 """ Class-based "Stage" API. requires instantiation (after derivation)
433 see "Stage API" above.. Note: python does *not* require derivation
434 from this class. All that is required is that the pipelines *have*
435 the functions listed in this class. Derivation from this class
436 is therefore merely a "courtesy" to maintainers.
439 def ispec(self
): pass # REQUIRED
441 def ospec(self
): pass # REQUIRED
443 #def setup(self, m, i): pass # OPTIONAL
445 def process(self
, i
): pass # REQUIRED
448 class Stage(metaclass
=ABCMeta
):
449 """ Static "Stage" API. does not require instantiation (after derivation)
451 see "Stage API" above. Note: python does *not* require derivation
452 from this class. All that is required is that the pipelines *have*
453 the functions listed in this class. Derivation from this class
454 is therefore merely a "courtesy" to maintainers.
466 #def setup(m, i): pass
473 class RecordBasedStage(Stage
):
474 """ convenience class which provides a Records-based layout.
475 honestly it's a lot easier just to create a direct Records-based
476 class (see ExampleAddRecordStage)
478 def __init__(self
, in_shape
, out_shape
, processfn
, setupfn
=None):
479 self
.in_shape
= in_shape
480 self
.out_shape
= out_shape
481 self
.__process
= processfn
482 self
.__setup
= setupfn
483 def ispec(self
): return Record(self
.in_shape
)
484 def ospec(self
): return Record(self
.out_shape
)
485 def process(seif
, i
): return self
.__process
(i
)
486 def setup(seif
, m
, i
): return self
.__setup
(m
, i
)
489 class StageChain(StageCls
):
490 """ pass in a list of stages, and they will automatically be
491 chained together via their input and output specs into a
494 the end result basically conforms to the exact same Stage API.
496 * input to this class will be the input of the first stage
497 * output of first stage goes into input of second
498 * output of second goes into input into third (etc. etc.)
499 * the output of this class will be the output of the last stage
501 def __init__(self
, chain
, specallocate
=False):
503 self
.specallocate
= specallocate
506 return self
.chain
[0].ispec()
509 return self
.chain
[-1].ospec()
511 def _specallocate_setup(self
, m
, i
):
512 for (idx
, c
) in enumerate(self
.chain
):
513 if hasattr(c
, "setup"):
514 c
.setup(m
, i
) # stage may have some module stuff
515 o
= self
.chain
[idx
].ospec() # last assignment survives
516 m
.d
.comb
+= eq(o
, c
.process(i
)) # process input into "o"
517 if idx
== len(self
.chain
)-1:
519 i
= self
.chain
[idx
+1].ispec() # new input on next loop
520 m
.d
.comb
+= eq(i
, o
) # assign to next input
521 return o
# last loop is the output
523 def _noallocate_setup(self
, m
, i
):
524 for (idx
, c
) in enumerate(self
.chain
):
525 if hasattr(c
, "setup"):
526 c
.setup(m
, i
) # stage may have some module stuff
527 i
= o
= c
.process(i
) # store input into "o"
528 return o
# last loop is the output
530 def setup(self
, m
, i
):
531 if self
.specallocate
:
532 self
.o
= self
._specallocate
_setup
(m
, i
)
534 self
.o
= self
._noallocate
_setup
(m
, i
)
536 def process(self
, i
):
537 return self
.o
# conform to Stage API: return last-loop output
541 """ Common functions for Pipeline API
543 def __init__(self
, stage
=None, in_multi
=None, stage_ctl
=False):
544 """ Base class containing ready/valid/data to previous and next stages
546 * p: contains ready/valid to the previous stage
547 * n: contains ready/valid to the next stage
549 Except when calling Controlbase.connect(), user must also:
550 * add i_data member to PrevControl (p) and
551 * add o_data member to NextControl (n)
555 # set up input and output IO ACK (prev/next ready/valid)
556 self
.p
= PrevControl(in_multi
, stage_ctl
)
557 self
.n
= NextControl(stage_ctl
)
559 # set up the input and output data
560 if stage
is not None:
561 self
.p
.i_data
= stage
.ispec() # input type
562 self
.n
.o_data
= stage
.ospec()
564 def connect_to_next(self
, nxt
):
565 """ helper function to connect to the next stage data/valid/ready.
567 return self
.n
.connect_to_next(nxt
.p
)
569 def _connect_in(self
, prev
):
570 """ internal helper function to connect stage to an input source.
571 do not use to connect stage-to-stage!
573 return self
.p
._connect
_in
(prev
.p
)
575 def _connect_out(self
, nxt
):
576 """ internal helper function to connect stage to an output source.
577 do not use to connect stage-to-stage!
579 return self
.n
._connect
_out
(nxt
.n
)
581 def connect(self
, pipechain
):
582 """ connects a chain (list) of Pipeline instances together and
583 links them to this ControlBase instance:
585 in <----> self <---> out
588 [pipe1, pipe2, pipe3, pipe4]
591 out---in out--in out---in
593 Also takes care of allocating i_data/o_data, by looking up
594 the data spec for each end of the pipechain. i.e It is NOT
595 necessary to allocate self.p.i_data or self.n.o_data manually:
596 this is handled AUTOMATICALLY, here.
598 Basically this function is the direct equivalent of StageChain,
599 except that unlike StageChain, the Pipeline logic is followed.
601 Just as StageChain presents an object that conforms to the
602 Stage API from a list of objects that also conform to the
603 Stage API, an object that calls this Pipeline connect function
604 has the exact same pipeline API as the list of pipline objects
607 Thus it becomes possible to build up larger chains recursively.
608 More complex chains (multi-input, multi-output) will have to be
611 eqs
= [] # collated list of assignment statements
613 # connect inter-chain
614 for i
in range(len(pipechain
)-1):
616 pipe2
= pipechain
[i
+1]
617 eqs
+= pipe1
.connect_to_next(pipe2
)
619 # connect front of chain to ourselves
621 self
.p
.i_data
= front
.stage
.ispec()
622 eqs
+= front
._connect
_in
(self
)
624 # connect end of chain to ourselves
626 self
.n
.o_data
= end
.stage
.ospec()
627 eqs
+= end
._connect
_out
(self
)
631 def _postprocess(self
, i
): # XXX DISABLED
632 return i
# RETURNS INPUT
633 if hasattr(self
.stage
, "postprocess"):
634 return self
.stage
.postprocess(i
)
637 def set_input(self
, i
):
638 """ helper function to set the input data
640 return eq(self
.p
.i_data
, i
)
643 res
= [self
.p
.i_valid
, self
.n
.i_ready
,
644 self
.n
.o_valid
, self
.p
.o_ready
,
646 if hasattr(self
.p
.i_data
, "ports"):
647 res
+= self
.p
.i_data
.ports()
650 if hasattr(self
.n
.o_data
, "ports"):
651 res
+= self
.n
.o_data
.ports()
656 def _elaborate(self
, platform
):
657 """ handles case where stage has dynamic ready/valid functions
661 if self
.stage
is not None and hasattr(self
.stage
, "setup"):
662 self
.stage
.setup(m
, self
.p
.i_data
)
664 if not self
.p
.stage_ctl
:
667 # intercept the previous (outgoing) "ready", combine with stage ready
668 m
.d
.comb
+= self
.p
.s_o_ready
.eq(self
.p
._o
_ready
& self
.stage
.d_ready
)
670 # intercept the next (incoming) "ready" and combine it with data valid
671 sdv
= self
.stage
.d_valid(self
.n
.i_ready
)
672 m
.d
.comb
+= self
.n
.d_valid
.eq(self
.n
.i_ready
& sdv
)
677 class BufferedHandshake(ControlBase
):
678 """ buffered pipeline stage. data and strobe signals travel in sync.
679 if ever the input is ready and the output is not, processed data
680 is shunted in a temporary register.
682 Argument: stage. see Stage API above
684 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
685 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
686 stage-1 p.i_data >>in stage n.o_data out>> stage+1
692 input data p.i_data is read (only), is processed and goes into an
693 intermediate result store [process()]. this is updated combinatorially.
695 in a non-stall condition, the intermediate result will go into the
696 output (update_output). however if ever there is a stall, it goes
697 into r_data instead [update_buffer()].
699 when the non-stall condition is released, r_data is the first
700 to be transferred to the output [flush_buffer()], and the stall
703 on the next cycle (as long as stall is not raised again) the
704 input may begin to be processed and transferred directly to output.
707 def elaborate(self
, platform
):
708 self
.m
= ControlBase
._elaborate
(self
, platform
)
710 result
= self
.stage
.ospec()
711 r_data
= self
.stage
.ospec()
713 # establish some combinatorial temporaries
714 o_n_validn
= Signal(reset_less
=True)
715 n_i_ready
= Signal(reset_less
=True, name
="n_i_rdy_data")
716 nir_por
= Signal(reset_less
=True)
717 nir_por_n
= Signal(reset_less
=True)
718 p_i_valid
= Signal(reset_less
=True)
719 nir_novn
= Signal(reset_less
=True)
720 nirn_novn
= Signal(reset_less
=True)
721 por_pivn
= Signal(reset_less
=True)
722 npnn
= Signal(reset_less
=True)
723 self
.m
.d
.comb
+= [p_i_valid
.eq(self
.p
.i_valid_test
),
724 o_n_validn
.eq(~self
.n
.o_valid
),
725 n_i_ready
.eq(self
.n
.i_ready_test
),
726 nir_por
.eq(n_i_ready
& self
.p
._o
_ready
),
727 nir_por_n
.eq(n_i_ready
& ~self
.p
._o
_ready
),
728 nir_novn
.eq(n_i_ready | o_n_validn
),
729 nirn_novn
.eq(~n_i_ready
& o_n_validn
),
730 npnn
.eq(nir_por | nirn_novn
),
731 por_pivn
.eq(self
.p
._o
_ready
& ~p_i_valid
)
734 # store result of processing in combinatorial temporary
735 self
.m
.d
.comb
+= eq(result
, self
.stage
.process(self
.p
.i_data
))
737 # if not in stall condition, update the temporary register
738 with self
.m
.If(self
.p
.o_ready
): # not stalled
739 self
.m
.d
.sync
+= eq(r_data
, result
) # update buffer
741 # data pass-through conditions
742 with self
.m
.If(npnn
):
743 o_data
= self
._postprocess
(result
)
744 self
.m
.d
.sync
+= [self
.n
.o_valid
.eq(p_i_valid
), # valid if p_valid
745 eq(self
.n
.o_data
, o_data
), # update output
747 # buffer flush conditions (NOTE: can override data passthru conditions)
748 with self
.m
.If(nir_por_n
): # not stalled
749 # Flush the [already processed] buffer to the output port.
750 o_data
= self
._postprocess
(r_data
)
751 self
.m
.d
.sync
+= [self
.n
.o_valid
.eq(1), # reg empty
752 eq(self
.n
.o_data
, o_data
), # flush buffer
754 # output ready conditions
755 self
.m
.d
.sync
+= self
.p
._o
_ready
.eq(nir_novn | por_pivn
)
760 class SimpleHandshake(ControlBase
):
761 """ simple handshake control. data and strobe signals travel in sync.
762 implements the protocol used by Wishbone and AXI4.
764 Argument: stage. see Stage API above
766 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
767 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
768 stage-1 p.i_data >>in stage n.o_data out>> stage+1
773 Inputs Temporary Output Data
774 ------- ---------- ----- ----
775 P P N N PiV& ~NiR& N P
782 0 0 1 0 0 0 0 1 process(i_data)
783 0 0 1 1 0 0 0 1 process(i_data)
787 0 1 1 0 0 0 0 1 process(i_data)
788 0 1 1 1 0 0 0 1 process(i_data)
792 1 0 1 0 0 0 0 1 process(i_data)
793 1 0 1 1 0 0 0 1 process(i_data)
795 1 1 0 0 1 0 1 0 process(i_data)
796 1 1 0 1 1 1 1 0 process(i_data)
797 1 1 1 0 1 0 1 1 process(i_data)
798 1 1 1 1 1 0 1 1 process(i_data)
802 def elaborate(self
, platform
):
803 self
.m
= m
= ControlBase
._elaborate
(self
, platform
)
806 result
= self
.stage
.ospec()
808 # establish some combinatorial temporaries
809 n_i_ready
= Signal(reset_less
=True, name
="n_i_rdy_data")
810 p_i_valid_p_o_ready
= Signal(reset_less
=True)
811 p_i_valid
= Signal(reset_less
=True)
812 m
.d
.comb
+= [p_i_valid
.eq(self
.p
.i_valid_test
),
813 n_i_ready
.eq(self
.n
.i_ready_test
),
814 p_i_valid_p_o_ready
.eq(p_i_valid
& self
.p
.o_ready
),
817 # store result of processing in combinatorial temporary
818 m
.d
.comb
+= eq(result
, self
.stage
.process(self
.p
.i_data
))
820 # previous valid and ready
821 with m
.If(p_i_valid_p_o_ready
):
822 o_data
= self
._postprocess
(result
)
823 m
.d
.sync
+= [r_busy
.eq(1), # output valid
824 eq(self
.n
.o_data
, o_data
), # update output
826 # previous invalid or not ready, however next is accepting
827 with m
.Elif(n_i_ready
):
828 o_data
= self
._postprocess
(result
)
829 m
.d
.sync
+= [eq(self
.n
.o_data
, o_data
)]
830 # TODO: could still send data here (if there was any)
831 #m.d.sync += self.n.o_valid.eq(0) # ...so set output invalid
832 m
.d
.sync
+= r_busy
.eq(0) # ...so set output invalid
834 m
.d
.comb
+= self
.n
.o_valid
.eq(r_busy
)
835 # if next is ready, so is previous
836 m
.d
.comb
+= self
.p
._o
_ready
.eq(n_i_ready
)
841 class UnbufferedPipeline(ControlBase
):
842 """ A simple pipeline stage with single-clock synchronisation
843 and two-way valid/ready synchronised signalling.
845 Note that a stall in one stage will result in the entire pipeline
848 Also that unlike BufferedHandshake, the valid/ready signalling does NOT
849 travel synchronously with the data: the valid/ready signalling
850 combines in a *combinatorial* fashion. Therefore, a long pipeline
851 chain will lengthen propagation delays.
853 Argument: stage. see Stage API, above
855 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
856 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
857 stage-1 p.i_data >>in stage n.o_data out>> stage+1
865 p.i_data : StageInput, shaped according to ispec
867 p.o_data : StageOutput, shaped according to ospec
869 r_data : input_shape according to ispec
870 A temporary (buffered) copy of a prior (valid) input.
871 This is HELD if the output is not ready. It is updated
873 result: output_shape according to ospec
874 The output of the combinatorial logic. it is updated
875 COMBINATORIALLY (no clock dependence).
879 Inputs Temp Output Data
901 1 1 0 0 0 1 1 process(i_data)
902 1 1 0 1 1 1 0 process(i_data)
903 1 1 1 0 0 1 1 process(i_data)
904 1 1 1 1 0 1 1 process(i_data)
907 Note: PoR is *NOT* involved in the above decision-making.
910 def elaborate(self
, platform
):
911 self
.m
= m
= ControlBase
._elaborate
(self
, platform
)
913 data_valid
= Signal() # is data valid or not
914 r_data
= self
.stage
.ospec() # output type
917 p_i_valid
= Signal(reset_less
=True)
918 pv
= Signal(reset_less
=True)
919 buf_full
= Signal(reset_less
=True)
920 m
.d
.comb
+= p_i_valid
.eq(self
.p
.i_valid_test
)
921 m
.d
.comb
+= pv
.eq(self
.p
.i_valid
& self
.p
.o_ready
)
922 m
.d
.comb
+= buf_full
.eq(~self
.n
.i_ready_test
& data_valid
)
924 m
.d
.comb
+= self
.n
.o_valid
.eq(data_valid
)
925 m
.d
.comb
+= self
.p
._o
_ready
.eq(~data_valid | self
.n
.i_ready_test
)
926 m
.d
.sync
+= data_valid
.eq(p_i_valid | buf_full
)
929 m
.d
.sync
+= eq(r_data
, self
.stage
.process(self
.p
.i_data
))
930 o_data
= self
._postprocess
(r_data
)
931 m
.d
.comb
+= eq(self
.n
.o_data
, o_data
)
935 class UnbufferedPipeline2(ControlBase
):
936 """ A simple pipeline stage with single-clock synchronisation
937 and two-way valid/ready synchronised signalling.
939 Note that a stall in one stage will result in the entire pipeline
942 Also that unlike BufferedHandshake, the valid/ready signalling does NOT
943 travel synchronously with the data: the valid/ready signalling
944 combines in a *combinatorial* fashion. Therefore, a long pipeline
945 chain will lengthen propagation delays.
947 Argument: stage. see Stage API, above
949 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
950 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
951 stage-1 p.i_data >>in stage n.o_data out>> stage+1
956 p.i_data : StageInput, shaped according to ispec
958 p.o_data : StageOutput, shaped according to ospec
960 buf : output_shape according to ospec
961 A temporary (buffered) copy of a valid output
962 This is HELD if the output is not ready. It is updated
965 Inputs Temp Output Data
967 P P N N ~NiR& N P (buf_full)
972 0 0 0 0 0 0 1 process(i_data)
973 0 0 0 1 1 1 0 reg (odata, unchanged)
974 0 0 1 0 0 0 1 process(i_data)
975 0 0 1 1 0 0 1 process(i_data)
977 0 1 0 0 0 0 1 process(i_data)
978 0 1 0 1 1 1 0 reg (odata, unchanged)
979 0 1 1 0 0 0 1 process(i_data)
980 0 1 1 1 0 0 1 process(i_data)
982 1 0 0 0 0 1 1 process(i_data)
983 1 0 0 1 1 1 0 reg (odata, unchanged)
984 1 0 1 0 0 1 1 process(i_data)
985 1 0 1 1 0 1 1 process(i_data)
987 1 1 0 0 0 1 1 process(i_data)
988 1 1 0 1 1 1 0 reg (odata, unchanged)
989 1 1 1 0 0 1 1 process(i_data)
990 1 1 1 1 0 1 1 process(i_data)
993 Note: PoR is *NOT* involved in the above decision-making.
996 def elaborate(self
, platform
):
997 self
.m
= m
= ControlBase
._elaborate
(self
, platform
)
999 buf_full
= Signal() # is data valid or not
1000 buf
= self
.stage
.ospec() # output type
1003 p_i_valid
= Signal(reset_less
=True)
1004 m
.d
.comb
+= p_i_valid
.eq(self
.p
.i_valid_test
)
1006 m
.d
.comb
+= self
.n
.o_valid
.eq(buf_full | p_i_valid
)
1007 m
.d
.comb
+= self
.p
._o
_ready
.eq(~buf_full
)
1008 m
.d
.sync
+= buf_full
.eq(~self
.n
.i_ready_test
& self
.n
.o_valid
)
1010 o_data
= Mux(buf_full
, buf
, self
.stage
.process(self
.p
.i_data
))
1011 o_data
= self
._postprocess
(o_data
)
1012 m
.d
.comb
+= eq(self
.n
.o_data
, o_data
)
1013 m
.d
.sync
+= eq(buf
, self
.n
.o_data
)
1018 class PassThroughStage(StageCls
):
1019 """ a pass-through stage which has its input data spec equal to its output,
1020 and "passes through" its data from input to output.
1022 def __init__(self
, iospecfn
):
1023 self
.iospecfn
= iospecfn
1024 def ispec(self
): return self
.iospecfn()
1025 def ospec(self
): return self
.iospecfn()
1026 def process(self
, i
): return i
1029 class PassThroughHandshake(ControlBase
):
1030 """ A control block that delays by one clock cycle.
1032 Inputs Temporary Output Data
1033 ------- ------------------ ----- ----
1034 P P N N PiV& PiV| NiR| pvr N P (pvr)
1035 i o i o PoR ~PoR ~NoV o o
1039 0 0 0 0 0 1 1 0 1 1 odata (unchanged)
1040 0 0 0 1 0 1 0 0 1 0 odata (unchanged)
1041 0 0 1 0 0 1 1 0 1 1 odata (unchanged)
1042 0 0 1 1 0 1 1 0 1 1 odata (unchanged)
1044 0 1 0 0 0 0 1 0 0 1 odata (unchanged)
1045 0 1 0 1 0 0 0 0 0 0 odata (unchanged)
1046 0 1 1 0 0 0 1 0 0 1 odata (unchanged)
1047 0 1 1 1 0 0 1 0 0 1 odata (unchanged)
1049 1 0 0 0 0 1 1 1 1 1 process(in)
1050 1 0 0 1 0 1 0 0 1 0 odata (unchanged)
1051 1 0 1 0 0 1 1 1 1 1 process(in)
1052 1 0 1 1 0 1 1 1 1 1 process(in)
1054 1 1 0 0 1 1 1 1 1 1 process(in)
1055 1 1 0 1 1 1 0 0 1 0 odata (unchanged)
1056 1 1 1 0 1 1 1 1 1 1 process(in)
1057 1 1 1 1 1 1 1 1 1 1 process(in)
1062 def elaborate(self
, platform
):
1063 self
.m
= m
= ControlBase
._elaborate
(self
, platform
)
1065 r_data
= self
.stage
.ospec() # output type
1068 p_i_valid
= Signal(reset_less
=True)
1069 pvr
= Signal(reset_less
=True)
1070 m
.d
.comb
+= p_i_valid
.eq(self
.p
.i_valid_test
)
1071 m
.d
.comb
+= pvr
.eq(p_i_valid
& self
.p
.o_ready
)
1073 m
.d
.comb
+= self
.p
.o_ready
.eq(~self
.n
.o_valid | self
.n
.i_ready_test
)
1074 m
.d
.sync
+= self
.n
.o_valid
.eq(p_i_valid | ~self
.p
.o_ready
)
1076 odata
= Mux(pvr
, self
.stage
.process(self
.p
.i_data
), r_data
)
1077 m
.d
.sync
+= eq(r_data
, odata
)
1078 r_data
= self
._postprocess
(r_data
)
1079 m
.d
.comb
+= eq(self
.n
.o_data
, r_data
)
1084 class RegisterPipeline(UnbufferedPipeline
):
1085 """ A pipeline stage that delays by one clock cycle, creating a
1086 sync'd latch out of o_data and o_valid as an indirect byproduct
1087 of using PassThroughStage
1089 def __init__(self
, iospecfn
):
1090 UnbufferedPipeline
.__init
__(self
, PassThroughStage(iospecfn
))
1093 class FIFOControl(ControlBase
):
1094 """ FIFO Control. Uses SyncFIFO to store data, coincidentally
1095 happens to have same valid/ready signalling as Stage API.
1097 i_data -> fifo.din -> FIFO -> fifo.dout -> o_data
1100 def __init__(self
, depth
, stage
, in_multi
=None, stage_ctl
=False,
1101 fwft
=True, buffered
=False, pipe
=False):
1104 * depth: number of entries in the FIFO
1105 * stage: data processing block
1106 * fwft : first word fall-thru mode (non-fwft introduces delay)
1107 * buffered: use buffered FIFO (introduces extra cycle delay)
1109 NOTE 1: FPGAs may have trouble with the defaults for SyncFIFO
1110 (fwft=True, buffered=False)
1112 NOTE 2: i_data *must* have a shape function. it can therefore
1113 be a Signal, or a Record, or a RecordObject.
1115 data is processed (and located) as follows:
1117 self.p self.stage temp fn temp fn temp fp self.n
1118 i_data->process()->result->cat->din.FIFO.dout->cat(o_data)
1120 yes, really: cat produces a Cat() which can be assigned to.
1121 this is how the FIFO gets de-catted without needing a de-cat
1125 assert not (fwft
and buffered
), "buffered cannot do fwft"
1129 self
.buffered
= buffered
1132 ControlBase
.__init
__(self
, stage
, in_multi
, stage_ctl
)
1134 def elaborate(self
, platform
):
1135 self
.m
= m
= ControlBase
._elaborate
(self
, platform
)
1137 # make a FIFO with a signal of equal width to the o_data.
1138 (fwidth
, _
) = self
.n
.o_data
.shape()
1140 fifo
= SyncFIFOBuffered(fwidth
, self
.fdepth
)
1142 fifo
= Queue(fwidth
, self
.fdepth
, fwft
=self
.fwft
, pipe
=self
.pipe
)
1143 m
.submodules
.fifo
= fifo
1145 # store result of processing in combinatorial temporary
1146 result
= self
.stage
.ospec()
1147 m
.d
.comb
+= eq(result
, self
.stage
.process(self
.p
.i_data
))
1149 # connect previous rdy/valid/data - do cat on i_data
1150 # NOTE: cannot do the PrevControl-looking trick because
1151 # of need to process the data. shaaaame....
1152 m
.d
.comb
+= [fifo
.we
.eq(self
.p
.i_valid_test
),
1153 self
.p
.o_ready
.eq(fifo
.writable
),
1154 eq(fifo
.din
, cat(result
)),
1157 # connect next rdy/valid/data - do cat on o_data
1158 connections
= [self
.n
.o_valid
.eq(fifo
.readable
),
1159 fifo
.re
.eq(self
.n
.i_ready_test
),
1161 if self
.fwft
or self
.buffered
:
1162 m
.d
.comb
+= connections
1164 m
.d
.sync
+= connections
# unbuffered fwft mode needs sync
1165 o_data
= cat(self
.n
.o_data
).eq(fifo
.dout
)
1166 o_data
= self
._postprocess
(o_data
)
1173 class UnbufferedPipeline(FIFOControl
):
1174 def __init__(self
, stage
, in_multi
=None, stage_ctl
=False):
1175 FIFOControl
.__init
__(self
, 1, stage
, in_multi
, stage_ctl
,
1176 fwft
=True, pipe
=False)
1178 # aka "BreakReadyStage" XXX had to set fwft=True to get it to work
1179 class PassThroughHandshake(FIFOControl
):
1180 def __init__(self
, stage
, in_multi
=None, stage_ctl
=False):
1181 FIFOControl
.__init
__(self
, 1, stage
, in_multi
, stage_ctl
,
1182 fwft
=True, pipe
=True)
1184 # this is *probably* BufferedHandshake, although test #997 now succeeds.
1185 class BufferedHandshake(FIFOControl
):
1186 def __init__(self
, stage
, in_multi
=None, stage_ctl
=False):
1187 FIFOControl
.__init
__(self
, 2, stage
, in_multi
, stage_ctl
,
1188 fwft
=True, pipe
=False)
1192 # this is *probably* SimpleHandshake (note: memory cell size=0)
1193 class SimpleHandshake(FIFOControl):
1194 def __init__(self, stage, in_multi=None, stage_ctl=False):
1195 FIFOControl.__init__(self, 0, stage, in_multi, stage_ctl,
1196 fwft=True, pipe=False)