62a5e641f8ae6f408a4f380f482033471877ccc6
1 """ Pipeline and BufferedPipeline implementation, conforming to the same API.
2 For multi-input and multi-output variants, see multipipe.
7 a strategically very important function that is identical in function
8 to nmigen's Signal.eq function, except it may take objects, or a list
9 of objects, or a tuple of objects, and where objects may also be
15 stage requires compliance with a strict API that may be
16 implemented in several means, including as a static class.
17 the methods of a stage instance must be as follows:
19 * ispec() - Input data format specification
20 returns an object or a list or tuple of objects, or
21 a Record, each object having an "eq" function which
22 takes responsibility for copying by assignment all
24 * ospec() - Output data format specification
25 requirements as for ospec
26 * process(m, i) - Processes an ispec-formatted object
27 returns a combinatorial block of a result that
28 may be assigned to the output, by way of the "eq"
30 * setup(m, i) - Optional function for setting up submodules
31 may be used for more complex stages, to link
32 the input (i) to submodules. must take responsibility
33 for adding those submodules to the module (m).
34 the submodules must be combinatorial blocks and
35 must have their inputs and output linked combinatorially.
37 Both StageCls (for use with non-static classes) and Stage (for use
38 by static classes) are abstract classes from which, for convenience
39 and as a courtesy to other developers, anything conforming to the
40 Stage API may *choose* to derive.
45 A useful combinatorial wrapper around stages that chains them together
46 and then presents a Stage-API-conformant interface. By presenting
47 the same API as the stages it wraps, it can clearly be used recursively.
52 A convenience class that takes an input shape, output shape, a
53 "processing" function and an optional "setup" function. Honestly
54 though, there's not much more effort to just... create a class
55 that returns a couple of Records (see ExampleAddRecordStage in
61 A convenience class that takes a single function as a parameter,
62 that is chain-called to create the exact same input and output spec.
63 It has a process() function that simply returns its input.
65 Instances of this class are completely redundant if handed to
66 StageChain, however when passed to UnbufferedPipeline they
67 can be used to introduce a single clock delay.
72 The base class for pipelines. Contains previous and next ready/valid/data.
73 Also has an extremely useful "connect" function that can be used to
74 connect a chain of pipelines and present the exact same prev/next
80 A simple stalling clock-synchronised pipeline that has no buffering
81 (unlike BufferedPipeline). Data flows on *every* clock cycle when
82 the conditions are right (this is nominally when the input is valid
83 and the output is ready).
85 A stall anywhere along the line will result in a stall back-propagating
86 down the entire chain. The BufferedPipeline by contrast will buffer
87 incoming data, allowing previous stages one clock cycle's grace before
90 An advantage of the UnbufferedPipeline over the Buffered one is
91 that the amount of logic needed (number of gates) is greatly
92 reduced (no second set of buffers basically)
94 The disadvantage of the UnbufferedPipeline is that the valid/ready
95 logic, if chained together, is *combinatorial*, resulting in
96 progressively larger gate delay.
101 A convenience class that, because UnbufferedPipeline introduces a single
102 clock delay, when its stage is a PassThroughStage, it results in a Pipeline
103 stage that, duh, delays its (unmodified) input by one clock cycle.
108 nmigen implementation of buffered pipeline stage, based on zipcpu:
109 https://zipcpu.com/blog/2017/08/14/strategies-for-pipelining.html
111 this module requires quite a bit of thought to understand how it works
112 (and why it is needed in the first place). reading the above is
113 *strongly* recommended.
115 unlike john dawson's IEEE754 FPU STB/ACK signalling, which requires
116 the STB / ACK signals to raise and lower (on separate clocks) before
117 data may proceeed (thus only allowing one piece of data to proceed
118 on *ALTERNATE* cycles), the signalling here is a true pipeline
119 where data will flow on *every* clock when the conditions are right.
121 input acceptance conditions are when:
122 * incoming previous-stage strobe (p.i_valid) is HIGH
123 * outgoing previous-stage ready (p.o_ready) is LOW
125 output transmission conditions are when:
126 * outgoing next-stage strobe (n.o_valid) is HIGH
127 * outgoing next-stage ready (n.i_ready) is LOW
129 the tricky bit is when the input has valid data and the output is not
130 ready to accept it. if it wasn't for the clock synchronisation, it
131 would be possible to tell the input "hey don't send that data, we're
132 not ready". unfortunately, it's not possible to "change the past":
133 the previous stage *has no choice* but to pass on its data.
135 therefore, the incoming data *must* be accepted - and stored: that
136 is the responsibility / contract that this stage *must* accept.
137 on the same clock, it's possible to tell the input that it must
138 not send any more data. this is the "stall" condition.
140 we now effectively have *two* possible pieces of data to "choose" from:
141 the buffered data, and the incoming data. the decision as to which
142 to process and output is based on whether we are in "stall" or not.
143 i.e. when the next stage is no longer ready, the output comes from
144 the buffer if a stall had previously occurred, otherwise it comes
145 direct from processing the input.
147 this allows us to respect a synchronous "travelling STB" with what
148 dan calls a "buffered handshake".
150 it's quite a complex state machine!
153 from nmigen
import Signal
, Cat
, Const
, Mux
, Module
, Value
154 from nmigen
.cli
import verilog
, rtlil
155 from nmigen
.hdl
.ast
import ArrayProxy
156 from nmigen
.hdl
.rec
import Record
, Layout
158 from abc
import ABCMeta
, abstractmethod
159 from collections
.abc
import Sequence
163 """ contains signals that come *from* the previous stage (both in and out)
164 * i_valid: previous stage indicating all incoming data is valid.
165 may be a multi-bit signal, where all bits are required
166 to be asserted to indicate "valid".
167 * o_ready: output to next stage indicating readiness to accept data
168 * i_data : an input - added by the user of this class
171 def __init__(self
, i_width
=1, stage_ctl
=False):
172 self
.stage_ctl
= stage_ctl
173 self
.i_valid
= Signal(i_width
, name
="p_i_valid") # prev >>in self
174 self
._o
_ready
= Signal(name
="p_o_ready") # prev <<out self
175 self
.i_data
= None # XXX MUST BE ADDED BY USER
177 self
.s_o_ready
= Signal(name
="p_s_o_rdy") # prev <<out self
181 """ public-facing API: indicates (externally) that stage is ready
184 return self
.s_o_ready
# set dynamically by stage
185 return self
._o
_ready
# return this when not under dynamic control
187 def _connect_in(self
, prev
):
188 """ internal helper function to connect stage to an input source.
189 do not use to connect stage-to-stage!
191 return [self
.i_valid
.eq(prev
.i_valid_test
),
192 prev
.o_ready
.eq(self
.o_ready
),
193 eq(self
.i_data
, prev
.i_data
),
197 def i_valid_test(self
):
198 vlen
= len(self
.i_valid
)
200 # multi-bit case: valid only when i_valid is all 1s
201 all1s
= Const(-1, (len(self
.i_valid
), False))
202 i_valid
= (self
.i_valid
== all1s
)
204 # single-bit i_valid case
205 i_valid
= self
.i_valid
207 # when stage indicates not ready, incoming data
208 # must "appear" to be not ready too
210 i_valid
= i_valid
& self
.s_o_ready
216 """ contains the signals that go *to* the next stage (both in and out)
217 * o_valid: output indicating to next stage that data is valid
218 * i_ready: input from next stage indicating that it can accept data
219 * o_data : an output - added by the user of this class
221 def __init__(self
, stage_ctl
=False):
222 self
.stage_ctl
= stage_ctl
223 self
.o_valid
= Signal(name
="n_o_valid") # self out>> next
224 self
.i_ready
= Signal(name
="n_i_ready") # self <<in next
225 self
.o_data
= None # XXX MUST BE ADDED BY USER
227 self
.d_valid
= Signal(reset
=1) # INTERNAL (data valid)
230 def i_ready_test(self
):
232 return self
.i_ready
& self
.d_valid
235 def connect_to_next(self
, nxt
):
236 """ helper function to connect to the next stage data/valid/ready.
237 data/valid is passed *TO* nxt, and ready comes *IN* from nxt.
238 use this when connecting stage-to-stage
240 return [nxt
.i_valid
.eq(self
.o_valid
),
241 self
.i_ready
.eq(nxt
.o_ready
),
242 eq(nxt
.i_data
, self
.o_data
),
245 def _connect_out(self
, nxt
):
246 """ internal helper function to connect stage to an output source.
247 do not use to connect stage-to-stage!
249 return [nxt
.o_valid
.eq(self
.o_valid
),
250 self
.i_ready
.eq(nxt
.i_ready_test
),
251 eq(nxt
.o_data
, self
.o_data
),
256 """ makes signals equal: a helper routine which identifies if it is being
257 passed a list (or tuple) of objects, or signals, or Records, and calls
258 the objects' eq function.
260 complex objects (classes) can be used: they must follow the
261 convention of having an eq member function, which takes the
262 responsibility of further calling eq and returning a list of
265 Record is a special (unusual, recursive) case, where the input may be
266 specified as a dictionary (which may contain further dictionaries,
267 recursively), where the field names of the dictionary must match
268 the Record's field spec. Alternatively, an object with the same
269 member names as the Record may be assigned: it does not have to
272 ArrayProxy is also special-cased, it's a bit messy: whilst ArrayProxy
273 has an eq function, the object being assigned to it (e.g. a python
274 object) might not. despite the *input* having an eq function,
275 that doesn't help us, because it's the *ArrayProxy* that's being
276 assigned to. so.... we cheat. use the ports() function of the
277 python object, enumerate them, find out the list of Signals that way,
281 if isinstance(o
, dict):
282 for (k
, v
) in o
.items():
283 print ("d-eq", v
, i
[k
])
284 res
.append(v
.eq(i
[k
]))
287 if not isinstance(o
, Sequence
):
289 for (ao
, ai
) in zip(o
, i
):
290 #print ("eq", ao, ai)
291 if isinstance(ao
, Record
):
292 for idx
, (field_name
, field_shape
, _
) in enumerate(ao
.layout
):
293 if isinstance(field_shape
, Layout
):
297 if hasattr(val
, field_name
): # check for attribute
298 val
= getattr(val
, field_name
)
300 val
= val
[field_name
] # dictionary-style specification
301 rres
= eq(ao
.fields
[field_name
], val
)
303 elif isinstance(ao
, ArrayProxy
) and not isinstance(ai
, Value
):
305 op
= getattr(ao
, p
.name
)
306 #print (op, p, p.name)
308 if not isinstance(rres
, Sequence
):
313 if not isinstance(rres
, Sequence
):
319 class StageCls(metaclass
=ABCMeta
):
320 """ Class-based "Stage" API. requires instantiation (after derivation)
322 see "Stage API" above.. Note: python does *not* require derivation
323 from this class. All that is required is that the pipelines *have*
324 the functions listed in this class. Derivation from this class
325 is therefore merely a "courtesy" to maintainers.
328 def ispec(self
): pass # REQUIRED
330 def ospec(self
): pass # REQUIRED
332 #def setup(self, m, i): pass # OPTIONAL
334 def process(self
, i
): pass # REQUIRED
337 class Stage(metaclass
=ABCMeta
):
338 """ Static "Stage" API. does not require instantiation (after derivation)
340 see "Stage API" above. Note: python does *not* require derivation
341 from this class. All that is required is that the pipelines *have*
342 the functions listed in this class. Derivation from this class
343 is therefore merely a "courtesy" to maintainers.
355 #def setup(m, i): pass
362 class RecordBasedStage(Stage
):
363 """ convenience class which provides a Records-based layout.
364 honestly it's a lot easier just to create a direct Records-based
365 class (see ExampleAddRecordStage)
367 def __init__(self
, in_shape
, out_shape
, processfn
, setupfn
=None):
368 self
.in_shape
= in_shape
369 self
.out_shape
= out_shape
370 self
.__process
= processfn
371 self
.__setup
= setupfn
372 def ispec(self
): return Record(self
.in_shape
)
373 def ospec(self
): return Record(self
.out_shape
)
374 def process(seif
, i
): return self
.__process
(i
)
375 def setup(seif
, m
, i
): return self
.__setup
(m
, i
)
378 class StageChain(StageCls
):
379 """ pass in a list of stages, and they will automatically be
380 chained together via their input and output specs into a
383 the end result basically conforms to the exact same Stage API.
385 * input to this class will be the input of the first stage
386 * output of first stage goes into input of second
387 * output of second goes into input into third (etc. etc.)
388 * the output of this class will be the output of the last stage
390 def __init__(self
, chain
, specallocate
=False):
392 self
.specallocate
= specallocate
395 return self
.chain
[0].ispec()
398 return self
.chain
[-1].ospec()
400 def setup(self
, m
, i
):
401 for (idx
, c
) in enumerate(self
.chain
):
402 if hasattr(c
, "setup"):
403 c
.setup(m
, i
) # stage may have some module stuff
404 if self
.specallocate
:
405 o
= self
.chain
[idx
].ospec() # last assignment survives
406 m
.d
.comb
+= eq(o
, c
.process(i
)) # process input into "o"
408 o
= c
.process(i
) # store input into "o"
409 if idx
!= len(self
.chain
)-1:
410 if self
.specallocate
:
411 ni
= self
.chain
[idx
+1].ispec() # new input on next loop
412 m
.d
.comb
+= eq(ni
, o
) # assign to next input
416 self
.o
= o
# last loop is the output
418 def process(self
, i
):
419 return self
.o
# conform to Stage API: return last-loop output
423 """ Common functions for Pipeline API
425 def __init__(self
, in_multi
=None, stage_ctl
=False):
426 """ Base class containing ready/valid/data to previous and next stages
428 * p: contains ready/valid to the previous stage
429 * n: contains ready/valid to the next stage
431 Except when calling Controlbase.connect(), user must also:
432 * add i_data member to PrevControl (p) and
433 * add o_data member to NextControl (n)
435 # set up input and output IO ACK (prev/next ready/valid)
436 self
.p
= PrevControl(in_multi
, stage_ctl
)
437 self
.n
= NextControl(stage_ctl
)
439 def connect_to_next(self
, nxt
):
440 """ helper function to connect to the next stage data/valid/ready.
442 return self
.n
.connect_to_next(nxt
.p
)
444 def _connect_in(self
, prev
):
445 """ internal helper function to connect stage to an input source.
446 do not use to connect stage-to-stage!
448 return self
.p
._connect
_in
(prev
.p
)
450 def _connect_out(self
, nxt
):
451 """ internal helper function to connect stage to an output source.
452 do not use to connect stage-to-stage!
454 return self
.n
._connect
_out
(nxt
.n
)
456 def connect(self
, pipechain
):
457 """ connects a chain (list) of Pipeline instances together and
458 links them to this ControlBase instance:
460 in <----> self <---> out
463 [pipe1, pipe2, pipe3, pipe4]
466 out---in out--in out---in
468 Also takes care of allocating i_data/o_data, by looking up
469 the data spec for each end of the pipechain. i.e It is NOT
470 necessary to allocate self.p.i_data or self.n.o_data manually:
471 this is handled AUTOMATICALLY, here.
473 Basically this function is the direct equivalent of StageChain,
474 except that unlike StageChain, the Pipeline logic is followed.
476 Just as StageChain presents an object that conforms to the
477 Stage API from a list of objects that also conform to the
478 Stage API, an object that calls this Pipeline connect function
479 has the exact same pipeline API as the list of pipline objects
482 Thus it becomes possible to build up larger chains recursively.
483 More complex chains (multi-input, multi-output) will have to be
486 eqs
= [] # collated list of assignment statements
488 # connect inter-chain
489 for i
in range(len(pipechain
)-1):
491 pipe2
= pipechain
[i
+1]
492 eqs
+= pipe1
.connect_to_next(pipe2
)
494 # connect front of chain to ourselves
496 self
.p
.i_data
= front
.stage
.ispec()
497 eqs
+= front
._connect
_in
(self
)
499 # connect end of chain to ourselves
501 self
.n
.o_data
= end
.stage
.ospec()
502 eqs
+= end
._connect
_out
(self
)
506 def set_input(self
, i
):
507 """ helper function to set the input data
509 return eq(self
.p
.i_data
, i
)
512 res
= [self
.p
.i_valid
, self
.n
.i_ready
,
513 self
.n
.o_valid
, self
.p
.o_ready
,
515 if hasattr(self
.p
.i_data
, "ports"):
516 res
+= self
.p
.i_data
.ports()
519 if hasattr(self
.n
.o_data
, "ports"):
520 res
+= self
.n
.o_data
.ports()
525 def _elaborate(self
, platform
):
526 """ handles case where stage has dynamic ready/valid functions
529 if not self
.p
.stage_ctl
:
532 # intercept the previous (outgoing) "ready", combine with stage ready
533 m
.d
.comb
+= self
.p
.s_o_ready
.eq(self
.p
._o
_ready
& self
.stage
.d_ready
)
535 # intercept the next (incoming) "ready" and combine it with data valid
536 m
.d
.comb
+= self
.n
.d_valid
.eq(self
.n
.i_ready
& self
.stage
.d_valid
)
541 class BufferedPipeline(ControlBase
):
542 """ buffered pipeline stage. data and strobe signals travel in sync.
543 if ever the input is ready and the output is not, processed data
544 is shunted in a temporary register.
546 Argument: stage. see Stage API above
548 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
549 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
550 stage-1 p.i_data >>in stage n.o_data out>> stage+1
556 input data p.i_data is read (only), is processed and goes into an
557 intermediate result store [process()]. this is updated combinatorially.
559 in a non-stall condition, the intermediate result will go into the
560 output (update_output). however if ever there is a stall, it goes
561 into r_data instead [update_buffer()].
563 when the non-stall condition is released, r_data is the first
564 to be transferred to the output [flush_buffer()], and the stall
567 on the next cycle (as long as stall is not raised again) the
568 input may begin to be processed and transferred directly to output.
571 def __init__(self
, stage
, stage_ctl
=False, buffermode
=True):
572 ControlBase
.__init
__(self
, stage_ctl
=stage_ctl
)
574 self
.buffermode
= buffermode
576 # set up the input and output data
577 self
.p
.i_data
= stage
.ispec() # input type
578 self
.n
.o_data
= stage
.ospec()
580 def elaborate(self
, platform
):
582 self
.m
= ControlBase
._elaborate
(self
, platform
)
584 result
= self
.stage
.ospec()
586 r_data
= self
.stage
.ospec()
587 if hasattr(self
.stage
, "setup"):
588 self
.stage
.setup(self
.m
, self
.p
.i_data
)
590 # establish some combinatorial temporaries
591 o_n_validn
= Signal(reset_less
=True)
592 n_i_ready
= Signal(reset_less
=True, name
="n_i_rdy_data")
593 i_p_valid_o_p_ready
= Signal(reset_less
=True)
594 p_i_valid
= Signal(reset_less
=True)
595 self
.m
.d
.comb
+= [p_i_valid
.eq(self
.p
.i_valid_test
),
596 o_n_validn
.eq(~self
.n
.o_valid
),
597 i_p_valid_o_p_ready
.eq(p_i_valid
& self
.p
.o_ready
),
598 n_i_ready
.eq(self
.n
.i_ready_test
),
601 # store result of processing in combinatorial temporary
602 self
.m
.d
.comb
+= eq(result
, self
.stage
.process(self
.p
.i_data
))
605 # if not in stall condition, update the temporary register
606 with self
.m
.If(self
.p
.o_ready
): # not stalled
607 self
.m
.d
.sync
+= eq(r_data
, result
) # update buffer
609 with self
.m
.If(n_i_ready
): # next stage is ready
610 with self
.m
.If(self
.p
._o
_ready
): # not stalled
611 # nothing in buffer: send (processed) input direct to output
612 self
.m
.d
.sync
+= [self
.n
.o_valid
.eq(p_i_valid
),
613 eq(self
.n
.o_data
, result
), # update output
616 with self
.m
.Else(): # p.o_ready is false, and data in buffer
617 # Flush the [already processed] buffer to the output port.
618 self
.m
.d
.sync
+= [self
.n
.o_valid
.eq(1), # reg empty
619 eq(self
.n
.o_data
, r_data
), # flush buffer
620 self
.p
._o
_ready
.eq(1), # clear stall
622 # ignore input, since p.o_ready is also false.
624 # (n.i_ready) is false here: next stage is ready
625 with self
.m
.Elif(o_n_validn
): # next stage being told "ready"
626 self
.m
.d
.sync
+= [self
.n
.o_valid
.eq(p_i_valid
),
627 self
.p
._o
_ready
.eq(1), # Keep the buffer empty
628 eq(self
.n
.o_data
, result
), # set output data
631 # (n.i_ready) false and (n.o_valid) true:
632 with self
.m
.Elif(i_p_valid_o_p_ready
):
633 # If next stage *is* ready, and not stalled yet, accept input
634 self
.m
.d
.sync
+= self
.p
._o
_ready
.eq(~
(p_i_valid
& self
.n
.o_valid
))
639 class BufferedPipeline2(ControlBase
):
640 """ buffered pipeline stage. data and strobe signals travel in sync.
641 if ever the input is ready and the output is not, processed data
642 is shunted in a temporary register.
644 Argument: stage. see Stage API above
646 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
647 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
648 stage-1 p.i_data >>in stage n.o_data out>> stage+1
654 input data p.i_data is read (only), is processed and goes into an
655 intermediate result store [process()]. this is updated combinatorially.
657 in a non-stall condition, the intermediate result will go into the
658 output (update_output). however if ever there is a stall, it goes
659 into r_data instead [update_buffer()].
661 when the non-stall condition is released, r_data is the first
662 to be transferred to the output [flush_buffer()], and the stall
665 on the next cycle (as long as stall is not raised again) the
666 input may begin to be processed and transferred directly to output.
669 def __init__(self
, stage
, stage_ctl
=False):
670 ControlBase
.__init
__(self
, stage_ctl
=stage_ctl
)
673 # set up the input and output data
674 self
.p
.i_data
= stage
.ispec() # input type
675 self
.n
.o_data
= stage
.ospec()
677 def elaborate(self
, platform
):
679 self
.m
= ControlBase
._elaborate
(self
, platform
)
681 result
= self
.stage
.ospec()
682 if hasattr(self
.stage
, "setup"):
683 self
.stage
.setup(self
.m
, self
.p
.i_data
)
685 # establish some combinatorial temporaries
686 n_i_ready
= Signal(reset_less
=True, name
="n_i_rdy_data")
687 p_i_valid_p_o_ready
= Signal(reset_less
=True)
688 p_i_valid
= Signal(reset_less
=True)
689 self
.m
.d
.comb
+= [p_i_valid
.eq(self
.p
.i_valid_test
),
690 n_i_ready
.eq(self
.n
.i_ready_test
),
691 p_i_valid_p_o_ready
.eq(p_i_valid
& self
.p
.o_ready
),
694 # store result of processing in combinatorial temporary
695 self
.m
.d
.comb
+= eq(result
, self
.stage
.process(self
.p
.i_data
))
697 # previous valid and ready
698 with self
.m
.If(p_i_valid_p_o_ready
):
699 self
.m
.d
.sync
+= [self
.n
.o_valid
.eq(1), # output valid
700 eq(self
.n
.o_data
, result
), # update output
702 # previous invalid or not ready, however next is accepting
703 with self
.m
.Elif(n_i_ready
):
704 # TODO: could still send data here (if there was any)
705 self
.m
.d
.sync
+= self
.n
.o_valid
.eq(0), # ...so set output invalid
707 # if next is ready, so is previous
708 self
.m
.d
.comb
+= self
.p
._o
_ready
.eq(n_i_ready
)
713 class UnbufferedPipeline(ControlBase
):
714 """ A simple pipeline stage with single-clock synchronisation
715 and two-way valid/ready synchronised signalling.
717 Note that a stall in one stage will result in the entire pipeline
720 Also that unlike BufferedPipeline, the valid/ready signalling does NOT
721 travel synchronously with the data: the valid/ready signalling
722 combines in a *combinatorial* fashion. Therefore, a long pipeline
723 chain will lengthen propagation delays.
725 Argument: stage. see Stage API, above
727 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
728 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
729 stage-1 p.i_data >>in stage n.o_data out>> stage+1
737 p.i_data : StageInput, shaped according to ispec
739 p.o_data : StageOutput, shaped according to ospec
741 r_data : input_shape according to ispec
742 A temporary (buffered) copy of a prior (valid) input.
743 This is HELD if the output is not ready. It is updated
745 result: output_shape according to ospec
746 The output of the combinatorial logic. it is updated
747 COMBINATORIALLY (no clock dependence).
750 def __init__(self
, stage
, stage_ctl
=False):
751 ControlBase
.__init
__(self
, stage_ctl
=stage_ctl
)
754 # set up the input and output data
755 self
.p
.i_data
= stage
.ispec() # input type
756 self
.n
.o_data
= stage
.ospec() # output type
758 def elaborate(self
, platform
):
759 self
.m
= ControlBase
._elaborate
(self
, platform
)
761 data_valid
= Signal() # is data valid or not
762 r_data
= self
.stage
.ispec() # input type
763 if hasattr(self
.stage
, "setup"):
764 self
.stage
.setup(self
.m
, r_data
)
767 p_i_valid
= Signal(reset_less
=True)
768 pv
= Signal(reset_less
=True)
769 self
.m
.d
.comb
+= p_i_valid
.eq(self
.p
.i_valid_test
)
770 self
.m
.d
.comb
+= pv
.eq(self
.p
.i_valid
& self
.p
.o_ready
)
772 self
.m
.d
.comb
+= self
.n
.o_valid
.eq(data_valid
)
773 self
.m
.d
.comb
+= self
.p
._o
_ready
.eq(~data_valid | self
.n
.i_ready_test
)
774 self
.m
.d
.sync
+= data_valid
.eq(p_i_valid | \
775 (~self
.n
.i_ready_test
& data_valid
))
777 self
.m
.d
.sync
+= eq(r_data
, self
.p
.i_data
)
778 self
.m
.d
.comb
+= eq(self
.n
.o_data
, self
.stage
.process(r_data
))
782 class UnbufferedPipeline2(ControlBase
):
783 """ A simple pipeline stage with single-clock synchronisation
784 and two-way valid/ready synchronised signalling.
786 Note that a stall in one stage will result in the entire pipeline
789 Also that unlike BufferedPipeline, the valid/ready signalling does NOT
790 travel synchronously with the data: the valid/ready signalling
791 combines in a *combinatorial* fashion. Therefore, a long pipeline
792 chain will lengthen propagation delays.
794 Argument: stage. see Stage API, above
796 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
797 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
798 stage-1 p.i_data >>in stage n.o_data out>> stage+1
806 p.i_data : StageInput, shaped according to ispec
808 p.o_data : StageOutput, shaped according to ospec
810 buf : output_shape according to ospec
811 A temporary (buffered) copy of a valid output
812 This is HELD if the output is not ready. It is updated
816 def __init__(self
, stage
, stage_ctl
=False):
817 ControlBase
.__init
__(self
, stage_ctl
=stage_ctl
)
820 # set up the input and output data
821 self
.p
.i_data
= stage
.ispec() # input type
822 self
.n
.o_data
= stage
.ospec() # output type
824 def elaborate(self
, platform
):
825 self
.m
= ControlBase
._elaborate
(self
, platform
)
827 buf_full
= Signal() # is data valid or not
828 buf
= self
.stage
.ospec() # output type
829 if hasattr(self
.stage
, "setup"):
830 self
.stage
.setup(self
.m
, self
.p
.i_data
)
833 p_i_valid
= Signal(reset_less
=True)
834 self
.m
.d
.comb
+= p_i_valid
.eq(self
.p
.i_valid_test
)
836 self
.m
.d
.comb
+= self
.n
.o_valid
.eq(buf_full | p_i_valid
)
837 self
.m
.d
.comb
+= self
.p
._o
_ready
.eq(~buf_full
)
838 self
.m
.d
.sync
+= buf_full
.eq(~self
.n
.i_ready_test
& \
839 (p_i_valid | buf_full
))
840 with self
.m
.If(buf_full
):
841 self
.m
.d
.comb
+= eq(self
.n
.o_data
, buf
)
843 self
.m
.d
.comb
+= eq(self
.n
.o_data
,
844 self
.stage
.process(self
.p
.i_data
))
845 self
.m
.d
.sync
+= eq(buf
, self
.n
.o_data
)
850 class PassThroughStage(StageCls
):
851 """ a pass-through stage which has its input data spec equal to its output,
852 and "passes through" its data from input to output.
854 def __init__(self
, iospecfn
):
855 self
.iospecfn
= iospecfn
856 def ispec(self
): return self
.iospecfn()
857 def ospec(self
): return self
.iospecfn()
858 def process(self
, i
): return i
861 class RegisterPipeline(UnbufferedPipeline
):
862 """ A pipeline stage that delays by one clock cycle, creating a
863 sync'd latch out of o_data and o_valid as an indirect byproduct
864 of using PassThroughStage
866 def __init__(self
, iospecfn
):
867 UnbufferedPipeline
.__init
__(self
, PassThroughStage(iospecfn
))