1 package slow_peripherals;
2 /*===== Project imports =====*/
3 import defined_types::*;
4 import AXI4_Lite_Fabric::*;
5 import AXI4_Lite_Types::*;
9 import AXI4Lite_AXI4_Bridge::*;
10 `include "instance_defines.bsv"
11 /* ==== define the AXI Addresses ==== */
13 /*====== AXI4 Lite slave declarations =======*/
16 /*===========================*/
17 /*=== package imports ===*/
20 import ClientServer::*;
21 import Connectable::*;
24 /*=======================*/
25 /*===== Import the slow peripherals ====*/
34 import axiexpansion ::*;
39 /*=====================================*/
41 /*===== interface declaration =====*/
42 interface SP_dedicated_ios;
44 interface Get#(Bit#(67)) axiexp1_out;
45 interface Put#(Bit#(67)) axiexp1_in;
48 interface Ifc_slow_peripherals;
49 interface AXI4_Slave_IFC#(`ADDR,`DATA,`USERSPACE) axi_slave;
50 interface SP_dedicated_ios slow_ios;
52 method Bit#(1) msip_int;
53 method Bit#(1) mtip_int;
54 method Bit#(`DATA) mtime;
56 `ifdef PLIC method ActionValue#(Tuple2#(Bool,Bool)) intrpt_note; `endif
57 interface IOCellSide iocell_side; // mandatory interface
60 /*================================*/
62 function Tuple2#(Bool, Bit#(TLog#(Num_Slow_Slaves)))
63 fn_address_mapping (Bit#(`ADDR) addr);
65 if(addr>=`ClintBase && addr<=`ClintEnd)
66 return tuple2(True,fromInteger(valueOf(CLINT_slave_num)));
70 if(addr>=`PLICBase && addr<=`PLICEnd)
71 return tuple2(True,fromInteger(valueOf(Plic_slave_num)));
75 if(addr>=`AxiExp1Base && addr<=`AxiExp1End)
76 return tuple2(True,fromInteger(valueOf(AxiExp1_slave_num)));
80 return tuple2(False,?);
84 module mkslow_peripherals#(Clock fast_clock, Reset fast_reset,
85 Clock uart_clock, Reset uart_reset
86 `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif
87 )(Ifc_slow_peripherals);
88 Clock sp_clock <-exposeCurrentClock; // slow peripheral clock
89 Reset sp_reset <-exposeCurrentReset; // slow peripheral reset
91 /*======= Module declarations for each peripheral =======*/
94 Ifc_clint clint <- mkclint();
97 Ifc_PLIC_AXI plic <- mkplicperipheral();
98 Wire#(Bit#(TLog#(`INTERRUPT_PINS))) interrupt_id <- mkWire();
99 Vector#(32, FIFO#(bit)) ff_gateway_queue <- replicateM(mkFIFO);
102 Ifc_AxiExpansion axiexp1 <- mkAxiExpansion();
104 Ifc_pinmux pinmux <- mkpinmux; // mandatory
105 /*=======================================================*/
107 AXI4_Lite_Fabric_IFC #(1, Num_Slow_Slaves, `ADDR, `DATA,`USERSPACE)
108 slow_fabric <- mkAXI4_Lite_Fabric(fn_address_mapping);
109 Ifc_AXI4Lite_AXI4_Bridge
110 bridge<-mkAXI4Lite_AXI4_Bridge(fast_clock,fast_reset);
112 mkConnection (bridge.axi4_lite_master, slow_fabric.v_from_masters [0]);
113 /*======= Slave connections to AXI4Lite fabric =========*/
116 mkConnection (slow_fabric.v_to_slaves
117 [fromInteger(valueOf(CLINT_slave_num))],
121 mkConnection (slow_fabric.v_to_slaves
122 [fromInteger(valueOf(Plic_slave_num))],
123 plic.axi4_slave_plic); //
126 mkConnection (slow_fabric.v_to_slaves
127 [fromInteger(valueOf(AxiExp1_slave_num))],
128 axiexp1.axi_slave); //
131 /*========== pinmux connections ============*/
134 rule rl_completion_msg_from_plic;
135 let id <- plic.intrpt_completion;
137 `ifdef verbose $display("Dequeing the FIFO -- PLIC Interrupt Serviced id: %d",id); `endif
140 for(Integer i=0; i <32; i=i+1) begin
141 rule deq_gateway_queue;
142 if(interrupt_id==fromInteger(i)) begin
143 ff_gateway_queue[i].deq;
144 `ifdef $display($time,"Dequeing the Interrupt request for ID: %d",i); `endif
148 /* for connectin inputs from pinmux as itnerrupts
149 rule connect_pinmux_eint;
150 wr_interrupt<= pinmux.peripheral_side.eint_input;
154 /*=======================================================*/
155 /*=================== PLIC Connections ==================== */
157 /*TODO DMA interrupt need to be connected to the plic
158 for(Integer i=1; i<8; i=i+1) begin
160 rule rl_connect_dma_interrupts_to_plic;
161 if(dma.interrupt_to_processor[i-1]==1'b1) begin
162 ff_gateway_queue[i].enq(1);
163 plic.ifc_external_irq[i].irq_frm_gateway(True);
167 rule rl_connect_dma_interrupts_to_plic;
168 ff_gateway_queue[i].enq(0);
173 rule rl_connect_i2c0_to_plic;
175 if(i2c0.isint()==1'b1) begin
176 ff_gateway_queue[8].enq(1);
177 plic.ifc_external_irq[8].irq_frm_gateway(True);
180 ff_gateway_queue[8].enq(0);
184 rule rl_connect_i2c1_to_plic;
186 if(i2c1.isint()==1'b1) begin
187 ff_gateway_queue[9].enq(1);
188 plic.ifc_external_irq[9].irq_frm_gateway(True);
191 ff_gateway_queue[9].enq(0);
195 rule rl_connect_i2c0_timerint_to_plic;
197 if(i2c0.timerint()==1'b1) begin
198 ff_gateway_queue[10].enq(1);
199 plic.ifc_external_irq[10].irq_frm_gateway(True);
202 ff_gateway_queue[10].enq(0);
206 rule rl_connect_i2c1_timerint_to_plic;
208 if(i2c1.timerint()==1'b1) begin
209 ff_gateway_queue[11].enq(1);
210 plic.ifc_external_irq[11].irq_frm_gateway(True);
213 ff_gateway_queue[11].enq(0);
217 rule rl_connect_i2c0_isber_to_plic;
219 if(i2c0.isber()==1'b1) begin
220 ff_gateway_queue[12].enq(1);
221 plic.ifc_external_irq[12].irq_frm_gateway(True);
224 ff_gateway_queue[12].enq(0);
228 rule rl_connect_i2c1_isber_to_plic;
230 if(i2c1.isber()==1'b1) begin
231 ff_gateway_queue[13].enq(1);
232 plic.ifc_external_irq[13].irq_frm_gateway(True);
235 ff_gateway_queue[13].enq(0);
239 for(Integer i = 14; i < 20; i=i+1) begin
240 rule rl_connect_qspi0_to_plic;
242 if(qspi0.interrupts()[i-14]==1'b1) begin
243 ff_gateway_queue[i].enq(1);
244 plic.ifc_external_irq[i].irq_frm_gateway(True);
247 ff_gateway_queue[i].enq(0);
252 for(Integer i = 20; i<26; i=i+1) begin
253 rule rl_connect_qspi1_to_plic;
255 if(qspi1.interrupts()[i-20]==1'b1) begin
256 ff_gateway_queue[i].enq(1);
257 plic.ifc_external_irq[i].irq_frm_gateway(True);
260 ff_gateway_queue[i].enq(0);
266 SyncBitIfc#(Bit#(1)) uart0_interrupt <-
267 mkSyncBitToCC(sp_clock, uart_reset);
268 rule synchronize_the_uart0_interrupt;
269 uart0_interrupt.send(uart0.irq);
272 rule rl_connect_uart_to_plic;
274 if(uart0_interrupt.read==1'b1) begin
275 ff_gateway_queue[27].enq(1);
276 plic.ifc_external_irq[27].irq_frm_gateway(True);
280 ff_gateway_queue[27].enq(0);
284 for(Integer i = 28; i<`INTERRUPT_PINS; i=i+1) begin
285 rule rl_raise_interrupts;
286 if((i-28)<`IONum) begin //Peripheral interrupts
287 if(gpio.to_plic[i-28]==1'b1) begin
288 plic.ifc_external_irq[i].irq_frm_gateway(True);
289 ff_gateway_queue[i].enq(1);
295 rule rl_completion_msg_from_plic;
296 let id <- plic.intrpt_completion;
298 `ifdef verbose $display("Dequeing the FIFO -- PLIC Interrupt Serviced id: %d",id); `endif
301 for(Integer i=0; i <`INTERRUPT_PINS; i=i+1) begin
302 rule deq_gateway_queue;
303 if(interrupt_id==fromInteger(i)) begin
304 ff_gateway_queue[i].deq;
305 `ifdef $display($time,"Dequeing the Interrupt request for ID: %d",i); `endif
312 /*======================================================= */
314 /* ===== interface definition =======*/
315 interface axi_slave=bridge.axi_slave;
316 `ifdef PLIC method intrpt_note = plic.intrpt_note; `endif
318 method msip_int=clint.msip_int;
319 method mtip_int=clint.mtip_int;
320 method mtime=clint.mtime;
323 method i2c0_isint=i2c0.isint;
326 method i2c1_isint=i2c1.isint;
328 `ifdef QSPI0 method qspi0_isint=qspi0.interrupts[5]; `endif
329 `ifdef QSPI1 method qspi1_isint=qspi1.interrupts[5]; `endif
330 `ifdef UART0 method uart0_intr=uart0.irq; `endif
331 interface SP_dedicated_ios slow_ios;
332 /* template for dedicated peripherals
334 interface uart0_coe=uart0.coe_rs232;
337 interface uart1_coe=uart1.coe_rs232;
340 interface i2c0_out=i2c0.out;
343 interface i2c1_out=i2c1.out;
346 interface qspi0_out = qspi0.out;
349 interface qspi1_out = qspi1.out;
352 interface axiexp1_out=axiexp1.slave_out;
353 interface axiexp1_in=axiexp1.slave_in;
356 interface pwm_o = pwm_bus.pwm_io;
361 interface iocell_side=pinmux.iocell_side;
362 interface pad_config0= gpioa.pad_config;
364 /*===================================*/