src/bsv/bsv_lib/slow_peripherals_template.bsv

   1 package slow_peripherals;
   2         /*===== Project imports =====*/
   3         import defined_types::*;
   4         import AXI4_Lite_Fabric::*;
   5         import AXI4_Lite_Types::*;
   6         import AXI4_Fabric::*;
   7         import AXI4_Types::*;
   8         import Semi_FIFOF::*;
   9         import AXI4Lite_AXI4_Bridge::*;
  10         `include "instance_defines.bsv"
  11     /* ==== define the AXI Addresses ==== */
  12 {2}
  13     /*====== AXI4 Lite slave declarations =======*/
  14
  15 {3}
  16         /*===========================*/
  17         /*=== package imports ===*/
  18         import Clocks::*;
  19         import GetPut::*;
  20         import ClientServer::*;
  21         import Connectable::*;
  22         import Vector::*;
  23         import FIFO::*;
  24         /*=======================*/
  25         /*===== Import the slow peripherals ====*/
  26 {0}
  27     `ifdef CLINT
  28         import clint::*;
  29     `endif
  30     `ifdef PLIC
  31         import plic             ::*;
  32     `endif
  33         `ifdef AXIEXP
  34                 import axiexpansion     ::*;
  35         `endif
  36         /*=====================================*/
  37
  38         /*===== interface declaration =====*/
  39         interface SP_ios;
  40 {1}
  41                 `ifdef AXIEXP
  42                         interface Get#(Bit#(67)) axiexp1_out;
  43                         interface Put#(Bit#(67)) axiexp1_in;
  44                 `endif
  45         endinterface
  46         interface Ifc_slow_peripherals;
  47                 interface AXI4_Slave_IFC#(`PADDR,`Reg_width,`USERSPACE) axi_slave;
  48                 interface SP_ios slow_ios;
  49     method Action external_int(Bit#(32) in);
  50                 `ifdef CLINT
  51                         method Bit#(1) msip_int;
  52                         method Bit#(1) mtip_int;
  53                         method Bit#(`Reg_width) mtime;
  54                 `endif
  55                 `ifdef PLIC method ActionValue#(Tuple2#(Bool,Bool)) intrpt_note; `endif
  56     interface IOCellSide iocell_side; // mandatory interface
  57         endinterface
  58         /*================================*/
  59
  60         function Tuple2#(Bool, Bit#(TLog#(Num_Slow_Slaves)))
  61                      fn_address_mapping (Bit#(`PADDR) addr);
  62                 `ifdef CLINT
  63                         if(addr>=`ClintBase && addr<=`ClintEnd)
  64                                 return tuple2(True,fromInteger(valueOf(CLINT_slave_num)));
  65                         else
  66                 `endif
  67                 `ifdef PLIC
  68                         if(addr>=`PLICBase && addr<=`PLICEnd)
  69                                 return tuple2(True,fromInteger(valueOf(Plic_slave_num)));
  70                         else
  71                 `endif
  72                 `ifdef AXIEXP
  73                         if(addr>=`AxiExp1Base && addr<=`AxiExp1End)
  74                                 return tuple2(True,fromInteger(valueOf(AxiExp1_slave_num)));
  75                         else
  76                 `endif
  77 {4}
  78                         return tuple2(False,?);
  79         endfunction
  80
  81         (*synthesize*)
  82         module mkslow_peripherals#(Clock fast_clock, Reset fast_reset,
  83                                Clock uart_clock, Reset uart_reset
  84                               `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif
  85                               )(Ifc_slow_peripherals);
  86                 Clock sp_clock <-exposeCurrentClock; // slow peripheral clock
  87                 Reset sp_reset <-exposeCurrentReset; // slow peripheral reset
  88
  89                 /*======= Module declarations for each peripheral =======*/
  90 {5}
  91                 `ifdef CLINT
  92                         Ifc_clint                               clint                           <- mkclint();
  93                 `endif
  94                 `ifdef PLIC
  95                         Ifc_PLIC_AXI    plic <- mkplicperipheral();
  96          Wire#(Bit#(TLog#(`INTERRUPT_PINS))) interrupt_id <- mkWire();
  97                           Vector#(32, FIFO#(bit)) ff_gateway_queue <- replicateM(mkFIFO);
  98                 `endif
  99                 `ifdef AXIEXP
 100                         Ifc_AxiExpansion                axiexp1                 <- mkAxiExpansion();
 101                 `endif
 102     Ifc_pinmux pinmux <- mkpinmux; // mandatory
 103     Wire#(Bit#(32)) wr_interrupt <- mkWire();
 104                 /*=======================================================*/
 105
 106         AXI4_Lite_Fabric_IFC #(1, Num_Slow_Slaves, `PADDR, `Reg_width,`USERSPACE)
 107             slow_fabric <- mkAXI4_Lite_Fabric(fn_address_mapping);
 108                 Ifc_AXI4Lite_AXI4_Bridge
 109             bridge<-mkAXI4Lite_AXI4_Bridge(fast_clock,fast_reset);
 110
 111                 mkConnection (bridge.axi4_lite_master,  slow_fabric.v_from_masters [0]);
 112                 /*======= Slave connections to AXI4Lite fabric =========*/
 113 {6}
 114                 `ifdef CLINT
 115                         mkConnection (slow_fabric.v_to_slaves
 116                     [fromInteger(valueOf(CLINT_slave_num))],
 117                     clint.axi4_slave);
 118                 `endif
 119                 `ifdef PLIC
 120                         mkConnection (slow_fabric.v_to_slaves
 121                     [fromInteger(valueOf(Plic_slave_num))],
 122                     plic.axi4_slave_plic); //
 123                 `endif
 124                 `ifdef AXIEXP
 125                 mkConnection (slow_fabric.v_to_slaves
 126                     [fromInteger(valueOf(AxiExp1_slave_num))],
 127                     axiexp1.axi_slave); //
 128                 `endif
 129
 130     /*========== pinmux connections ============*/
 131 {7}
 132 {8}
 133     rule connect_i2c0_scl;
 134       pinmux.peripheral_side.twi_scl_out(i2c0.out.scl_out);
 135       pinmux.peripheral_side.twi_scl_outen(pack(i2c0.out.scl_out_en));
 136     endrule
 137     rule connect_i2c0_scl_in;
 138       i2c0.out.scl_in(pinmux.peripheral_side.twi_scl_in);
 139     endrule
 140     rule connect_i2c0_sda;
 141       pinmux.peripheral_side.twi_sda_out(i2c0.out.sda_out);
 142       pinmux.peripheral_side.twi_sda_outen(pack(i2c0.out.sda_out_en));
 143     endrule
 144     rule connect_i2c0_sda_in;
 145       i2c0.out.sda_in(pinmux.peripheral_side.twi_sda_in);
 146     endrule
 147     rule connect_uart1tx;
 148       pinmux.peripheral_side.uart_tx(uart1.coe_rs232.sout);
 149     endrule
 150     rule connect_uart1rx;
 151       uart1.coe_rs232.sin(pinmux.peripheral_side.uart_rx);
 152     endrule
 153     for(Integer i=0;i<32;i=i+ 1)begin
 154       rule connect_int_to_plic(wr_interrupt[i]==1);
 155                                 ff_gateway_queue[i].enq(1);
 156                                 plic.ifc_external_irq[i].irq_frm_gateway(True);
 157       endrule
 158     end
 159     rule rl_completion_msg_from_plic;
 160                   let id <- plic.intrpt_completion;
 161       interrupt_id <= id;
 162       `ifdef verbose $display("Dequeing the FIFO -- PLIC Interrupt Serviced id: %d",id); `endif
 163                 endrule
 164
 165     for(Integer i=0; i <32; i=i+1) begin
 166             rule deq_gateway_queue;
 167                     if(interrupt_id==fromInteger(i)) begin
 168                             ff_gateway_queue[i].deq;
 169           `ifdef $display($time,"Dequeing the Interrupt request for ID: %d",i); `endif
 170         end
 171       endrule
 172     end
 173     /* for connectin inputs from pinmux as itnerrupts
 174       rule connect_pinmux_eint;
 175         wr_interrupt<= pinmux.peripheral_side.eint_input;
 176       endrule
 177     */
 178     // NEEL EDIT OVER
 179                 /*=======================================================*/
 180                 /*=================== PLIC Connections ==================== */
 181                 `ifdef PLIC_main
 182                         /*TODO DMA interrupt need to be connected to the plic
 183                         for(Integer i=1; i<8; i=i+1) begin
 184          `ifdef DMA
 185              rule rl_connect_dma_interrupts_to_plic;
 186                                         if(dma.interrupt_to_processor[i-1]==1'b1) begin
 187                                                 ff_gateway_queue[i].enq(1);
 188                                                 plic.ifc_external_irq[i].irq_frm_gateway(True);
 189                                         end
 190              endrule
 191           `else
 192              rule rl_connect_dma_interrupts_to_plic;
 193                  ff_gateway_queue[i].enq(0);
 194              endrule
 195           `endif
 196          end
 197                         */
 198          rule rl_connect_i2c0_to_plic;
 199                                 `ifdef I2C0
 200                                         if(i2c0.isint()==1'b1) begin
 201                                                 ff_gateway_queue[8].enq(1);
 202                                                 plic.ifc_external_irq[8].irq_frm_gateway(True);
 203                                         end
 204                                 `else
 205                                         ff_gateway_queue[8].enq(0);
 206             `endif
 207          endrule
 208
 209                         rule rl_connect_i2c1_to_plic;
 210                                 `ifdef I2C1
 211                                         if(i2c1.isint()==1'b1) begin
 212                                                 ff_gateway_queue[9].enq(1);
 213                                                 plic.ifc_external_irq[9].irq_frm_gateway(True);
 214                                         end
 215             `else
 216                                         ff_gateway_queue[9].enq(0);
 217             `endif
 218                         endrule
 219
 220          rule rl_connect_i2c0_timerint_to_plic;
 221                                 `ifdef I2C0
 222                                         if(i2c0.timerint()==1'b1) begin
 223                                                 ff_gateway_queue[10].enq(1);
 224                                                 plic.ifc_external_irq[10].irq_frm_gateway(True);
 225                                         end
 226             `else
 227                                         ff_gateway_queue[10].enq(0);
 228             `endif
 229                         endrule
 230
 231          rule rl_connect_i2c1_timerint_to_plic;
 232                                 `ifdef I2C1
 233                                         if(i2c1.timerint()==1'b1) begin
 234                                                 ff_gateway_queue[11].enq(1);
 235                                                 plic.ifc_external_irq[11].irq_frm_gateway(True);
 236                                         end
 237             `else
 238                                         ff_gateway_queue[11].enq(0);
 239             `endif
 240          endrule
 241
 242          rule rl_connect_i2c0_isber_to_plic;
 243                                 `ifdef I2C0
 244                                         if(i2c0.isber()==1'b1) begin
 245                                                 ff_gateway_queue[12].enq(1);
 246                                                 plic.ifc_external_irq[12].irq_frm_gateway(True);
 247                                         end
 248             `else
 249                                         ff_gateway_queue[12].enq(0);
 250             `endif
 251          endrule
 252
 253          rule rl_connect_i2c1_isber_to_plic;
 254                                 `ifdef I2C1
 255                                         if(i2c1.isber()==1'b1) begin
 256                                                 ff_gateway_queue[13].enq(1);
 257                                                 plic.ifc_external_irq[13].irq_frm_gateway(True);
 258                end
 259             `else
 260                                         ff_gateway_queue[13].enq(0);
 261             `endif
 262          endrule
 263
 264          for(Integer i = 14; i < 20; i=i+1) begin
 265                                 rule rl_connect_qspi0_to_plic;
 266                                         `ifdef QSPI0
 267                                                 if(qspi0.interrupts()[i-14]==1'b1) begin
 268                                                         ff_gateway_queue[i].enq(1);
 269                                                         plic.ifc_external_irq[i].irq_frm_gateway(True);
 270                                                 end
 271                `else
 272                                                 ff_gateway_queue[i].enq(0);
 273                `endif
 274             endrule
 275          end
 276
 277          for(Integer i = 20; i<26; i=i+1) begin
 278                                 rule rl_connect_qspi1_to_plic;
 279                                         `ifdef QSPI1
 280                                                 if(qspi1.interrupts()[i-20]==1'b1) begin
 281                                                         ff_gateway_queue[i].enq(1);
 282                                                         plic.ifc_external_irq[i].irq_frm_gateway(True);
 283                                                 end
 284                `else
 285                                                 ff_gateway_queue[i].enq(0);
 286                `endif
 287             endrule
 288                         end
 289
 290                         `ifdef UART0
 291                                 SyncBitIfc#(Bit#(1)) uart0_interrupt <-mkSyncBitToCC(uart_clock,uart_reset);
 292                                 rule synchronize_the_uart0_interrupt;
 293                                         uart0_interrupt.send(uart0.irq);
 294                                 endrule
 295                         `endif
 296                         rule rl_connect_uart_to_plic;
 297                                 `ifdef UART0
 298                                         if(uart0_interrupt.read==1'b1) begin
 299                                                 ff_gateway_queue[27].enq(1);
 300                                                 plic.ifc_external_irq[27].irq_frm_gateway(True);
 301                end
 302
 303             `else
 304                                         ff_gateway_queue[27].enq(0);
 305             `endif
 306          endrule
 307
 308                         for(Integer i = 28; i<`INTERRUPT_PINS; i=i+1) begin
 309                                 rule rl_raise_interrupts;
 310                                         if((i-28)<`IONum) begin //Peripheral interrupts
 311                                                 if(gpio.to_plic[i-28]==1'b1) begin
 312                                                         plic.ifc_external_irq[i].irq_frm_gateway(True);
 313                                                                 ff_gateway_queue[i].enq(1);
 314                   end
 315                                         end
 316                                 endrule
 317                         end
 318
 319          rule rl_completion_msg_from_plic;
 320                                 let id <- plic.intrpt_completion;
 321             interrupt_id <= id;
 322             `ifdef verbose $display("Dequeing the FIFO -- PLIC Interrupt Serviced id: %d",id); `endif
 323                         endrule
 324
 325          for(Integer i=0; i <`INTERRUPT_PINS; i=i+1) begin
 326                                 rule deq_gateway_queue;
 327                                         if(interrupt_id==fromInteger(i)) begin
 328                                                 ff_gateway_queue[i].deq;
 329                   `ifdef $display($time,"Dequeing the Interrupt request for ID: %d",i); `endif
 330                end
 331             endrule
 332          end
 333
 334
 335                 `endif
 336                         /*======================================================= */
 337
 338                 /* ===== interface definition =======*/
 339                 interface axi_slave=bridge.axi_slave;
 340                 `ifdef PLIC method intrpt_note = plic.intrpt_note; `endif
 341                 `ifdef CLINT
 342                         method msip_int=clint.msip_int;
 343                         method mtip_int=clint.mtip_int;
 344                         method mtime=clint.mtime;
 345                 `endif
 346                 `ifdef I2C0
 347                         method i2c0_isint=i2c0.isint;
 348                 `endif
 349                 `ifdef I2C1
 350                         method i2c1_isint=i2c1.isint;
 351                 `endif
 352                 `ifdef QSPI0 method     qspi0_isint=qspi0.interrupts[5]; `endif
 353                 `ifdef QSPI1 method     qspi1_isint=qspi1.interrupts[5]; `endif
 354                 `ifdef UART0 method uart0_intr=uart0.irq; `endif
 355                 interface SP_ios slow_ios;
 356                         `ifdef UART0
 357                                 interface uart0_coe=uart0.coe_rs232;
 358                         `endif
 359                         `ifdef UART1
 360                                 interface uart1_coe=uart1.coe_rs232;
 361                         `endif
 362                         `ifdef I2C0
 363                                 interface i2c0_out=i2c0.out;
 364                         `endif
 365                         `ifdef I2C1
 366                                 interface i2c1_out=i2c1.out;
 367                         `endif
 368                         `ifdef QSPI0
 369                                 interface qspi0_out = qspi0.out;
 370                         `endif
 371                         `ifdef QSPI1
 372                                 interface qspi1_out = qspi1.out;
 373                         `endif
 374                         `ifdef AXIEXP
 375                                 interface axiexp1_out=axiexp1.slave_out;
 376                                 interface axiexp1_in=axiexp1.slave_in;
 377                         `endif
 378       `ifdef PWM_AXI4Lite
 379         interface pwm_o = pwm_bus.pwm_io;
 380       `endif
 381                 endinterface
 382     // NEEL EDIT
 383     interface iocell_side=pinmux.iocell_side;
 384     interface pad_configa= gpioa.pad_config;
 385     method Action external_int(Bit#(32) in);
 386       wr_interrupt<= in;
 387     endmethod
 388     // NEEL EDIT OVER
 389                 /*===================================*/
 390         endmodule
 391 endpackage