src/bsv/bsv_lib/slow_peripherals_template.bsv

   1 package slow_peripherals;
   2         /*===== Project imports =====*/
   3         import defined_types::*;
   4         import AXI4_Lite_Fabric::*;
   5         import AXI4_Lite_Types::*;
   6         import AXI4_Fabric::*;
   7         import AXI4_Types::*;
   8         import Semi_FIFOF::*;
   9         import AXI4Lite_AXI4_Bridge::*;
  10         `include "instance_defines.bsv"
  11     /* ==== define the AXI Addresses ==== */
  12 {2}
  13     /*====== AXI4 Lite slave declarations =======*/
  14
  15 {3}
  16         /*===========================*/
  17         /*=== package imports ===*/
  18         import Clocks::*;
  19         import GetPut::*;
  20         import ClientServer::*;
  21         import Connectable::*;
  22         import Vector::*;
  23         import FIFO::*;
  24         /*=======================*/
  25         /*===== Import the slow peripherals ====*/
  26 {0}
  27     `ifdef CLINT
  28         import clint::*;
  29     `endif
  30     `ifdef PLIC
  31         import plic             ::*;
  32     `endif
  33         `ifdef AXIEXP
  34                 import axiexpansion     ::*;
  35         `endif
  36         /*=====================================*/
  37
  38         /*===== interface declaration =====*/
  39         interface SP_ios;
  40 {1}
  41                 `ifdef AXIEXP
  42                         interface Get#(Bit#(67)) axiexp1_out;
  43                         interface Put#(Bit#(67)) axiexp1_in;
  44                 `endif
  45         endinterface
  46         interface Ifc_slow_peripherals;
  47                 interface AXI4_Slave_IFC#(`PADDR,`Reg_width,`USERSPACE) axi_slave;
  48                 interface SP_ios slow_ios;
  49     method Action external_int(Bit#(32) in);
  50                 `ifdef CLINT
  51                         method Bit#(1) msip_int;
  52                         method Bit#(1) mtip_int;
  53                         method Bit#(`Reg_width) mtime;
  54                 `endif
  55                 `ifdef PLIC method ActionValue#(Tuple2#(Bool,Bool)) intrpt_note; `endif
  56     interface IOCellSide iocell_side; // mandatory interface
  57         endinterface
  58         /*================================*/
  59
  60         function Tuple2#(Bool, Bit#(TLog#(Num_Slow_Slaves)))
  61                      fn_address_mapping (Bit#(`PADDR) addr);
  62                 `ifdef CLINT
  63                         if(addr>=`ClintBase && addr<=`ClintEnd)
  64                                 return tuple2(True,fromInteger(valueOf(CLINT_slave_num)));
  65                         else
  66                 `endif
  67                 `ifdef PLIC
  68                         if(addr>=`PLICBase && addr<=`PLICEnd)
  69                                 return tuple2(True,fromInteger(valueOf(Plic_slave_num)));
  70                         else
  71                 `endif
  72                 `ifdef AXIEXP
  73                         if(addr>=`AxiExp1Base && addr<=`AxiExp1End)
  74                                 return tuple2(True,fromInteger(valueOf(AxiExp1_slave_num)));
  75                         else
  76                 `endif
  77 {4}
  78                         return tuple2(False,?);
  79         endfunction
  80
  81         (*synthesize*)
  82         module mkslow_peripherals#(Clock fast_clock, Reset fast_reset,
  83                                Clock uart_clock, Reset uart_reset
  84   `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif
  85                               )(Ifc_slow_peripherals);
  86                 Clock sp_clock <-exposeCurrentClock; // slow peripheral clock
  87                 Reset sp_reset <-exposeCurrentReset; // slow peripheral reset
  88
  89                 /*======= Module declarations for each peripheral =======*/
  90 {5}
  91                 `ifdef CLINT
  92                         Ifc_clint                               clint                           <- mkclint();
  93                 `endif
  94                 `ifdef PLIC
  95                         Ifc_PLIC_AXI    plic <- mkplicperipheral();
  96          Wire#(Bit#(TLog#(`INTERRUPT_PINS))) interrupt_id <- mkWire();
  97                           Vector#(32, FIFO#(bit)) ff_gateway_queue <- replicateM(mkFIFO);
  98                 `endif
  99                 `ifdef AXIEXP
 100                         Ifc_AxiExpansion                axiexp1                 <- mkAxiExpansion();
 101                 `endif
 102     Ifc_pinmux pinmux <- mkpinmux; // mandatory
 103     Wire#(Bit#(32)) wr_interrupt <- mkWire();
 104                 /*=======================================================*/
 105
 106         AXI4_Lite_Fabric_IFC #(1, Num_Slow_Slaves, `PADDR, `Reg_width,`USERSPACE)       slow_fabric <-
 107                                                             mkAXI4_Lite_Fabric(fn_address_mapping);
 108                 Ifc_AXI4Lite_AXI4_Bridge bridge <-mkAXI4Lite_AXI4_Bridge(fast_clock,fast_reset);
 109
 110                 mkConnection (bridge.axi4_lite_master,  slow_fabric.v_from_masters [0]);
 111                 /*======= Slave connections to AXI4Lite fabric =========*/
 112                 `ifdef UART0
 113                         mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(Uart0_slave_num))],
 114                     uart0.slave_axi_uart);
 115                 `endif
 116                 `ifdef UART1
 117                 mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(Uart1_slave_num))],
 118                     uart1.slave_axi_uart);
 119                 `endif
 120                 `ifdef CLINT
 121                         mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(CLINT_slave_num))],
 122                     clint.axi4_slave);
 123                 `endif
 124                 `ifdef PLIC
 125                         mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(Plic_slave_num))],
 126                     plic.axi4_slave_plic); //
 127                 `endif
 128                 `ifdef I2C0
 129                 mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(I2c0_slave_num))],
 130                     i2c0.slave_i2c_axi);
 131                 `endif
 132                 `ifdef I2C1
 133                 mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(I2c1_slave_num))],
 134                     i2c1.slave_i2c_axi); //
 135                 `endif
 136                 `ifdef QSPI0
 137                         mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(Qspi0_slave_num))],
 138                     qspi0.slave);
 139                 `endif
 140                 `ifdef QSPI1
 141                         mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(Qspi1_slave_num))],
 142                     qspi1.slave);
 143                 `endif
 144                 `ifdef AXIEXP
 145                 mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(AxiExp1_slave_num))],
 146                     axiexp1.axi_slave); //
 147                 `endif
 148     `ifdef PWM_AXI4Lite
 149       mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(Pwm_slave_num))],
 150                     pwm_bus.axi4_slave);
 151     `endif
 152
 153     // NEEL EDIT
 154     mkConnection (slow_fabric.
 155                   v_to_slaves[fromInteger(valueOf(Muxa_slave_num))],
 156                   muxa.axi_slave);
 157     mkConnection (slow_fabric.
 158                   v_to_slaves[fromInteger(valueOf(Gpioa_slave_num))],
 159                   gpioa.axi_slave);
 160     rule connect_select_lines_pinmux;// mandatory
 161       pinmux.mux_lines.cell0_mux(muxa.mux_config.mux[0]);
 162       pinmux.mux_lines.cell1_mux(muxa.mux_config.mux[1]);
 163       pinmux.mux_lines.cell2_mux(muxa.mux_config.mux[2]);
 164     endrule
 165     rule connect_i2c0_scl;
 166       pinmux.peripheral_side.twi_scl_out(i2c0.out.scl_out);
 167       pinmux.peripheral_side.twi_scl_outen(pack(i2c0.out.scl_out_en));
 168     endrule
 169     rule connect_i2c0_scl_in;
 170       i2c0.out.scl_in(pinmux.peripheral_side.twi_scl_in);
 171     endrule
 172     rule connect_i2c0_sda;
 173       pinmux.peripheral_side.twi_sda_out(i2c0.out.sda_out);
 174       pinmux.peripheral_side.twi_sda_outen(pack(i2c0.out.sda_out_en));
 175     endrule
 176     rule connect_i2c0_sda_in;
 177       i2c0.out.sda_in(pinmux.peripheral_side.twi_sda_in);
 178     endrule
 179     rule connect_uart1tx;
 180       pinmux.peripheral_side.uart_tx(uart1.coe_rs232.sout);
 181     endrule
 182     rule connect_uart1rx;
 183       uart1.coe_rs232.sin(pinmux.peripheral_side.uart_rx);
 184     endrule
 185     rule connect_gpioa;
 186       pinmux.peripheral_side.gpioa_a0_out(gpioa.func.gpio_out[0]);
 187       pinmux.peripheral_side.gpioa_a0_outen(gpioa.func.gpio_out_en[0]);
 188       pinmux.peripheral_side.gpioa_a1_out(gpioa.func.gpio_out[1]);
 189       pinmux.peripheral_side.gpioa_a1_outen(gpioa.func.gpio_out_en[1]);
 190       pinmux.peripheral_side.gpioa_a2_out(gpioa.func.gpio_out[2]);
 191       pinmux.peripheral_side.gpioa_a2_outen(gpioa.func.gpio_out_en[2]);
 192                 Vector#(3,Bit#(1)) temp;
 193                 temp[0]=pinmux.peripheral_side.gpioa_a0_in;
 194                 temp[1]=pinmux.peripheral_side.gpioa_a1_in;
 195                 temp[2]=pinmux.peripheral_side.gpioa_a2_in;
 196       gpioa.func.gpio_in(temp);
 197     endrule
 198     for(Integer i=0;i<32;i=i+ 1)begin
 199       rule connect_int_to_plic(wr_interrupt[i]==1);
 200                                 ff_gateway_queue[i].enq(1);
 201                                 plic.ifc_external_irq[i].irq_frm_gateway(True);
 202       endrule
 203     end
 204     rule rl_completion_msg_from_plic;
 205                   let id <- plic.intrpt_completion;
 206       interrupt_id <= id;
 207       `ifdef verbose $display("Dequeing the FIFO -- PLIC Interrupt Serviced id: %d",id); `endif
 208                 endrule
 209
 210     for(Integer i=0; i <32; i=i+1) begin
 211             rule deq_gateway_queue;
 212                     if(interrupt_id==fromInteger(i)) begin
 213                             ff_gateway_queue[i].deq;
 214           `ifdef $display($time,"Dequeing the Interrupt request for ID: %d",i); `endif
 215         end
 216       endrule
 217     end
 218     /* for connectin inputs from pinmux as itnerrupts
 219       rule connect_pinmux_eint;
 220         wr_interrupt<= pinmux.peripheral_side.eint_input;
 221       endrule
 222     */
 223     // NEEL EDIT OVER
 224                 /*=======================================================*/
 225                 /*=================== PLIC Connections ==================== */
 226                 `ifdef PLIC_main
 227                         /*TODO DMA interrupt need to be connected to the plic
 228                         for(Integer i=1; i<8; i=i+1) begin
 229          `ifdef DMA
 230              rule rl_connect_dma_interrupts_to_plic;
 231                                         if(dma.interrupt_to_processor[i-1]==1'b1) begin
 232                                                 ff_gateway_queue[i].enq(1);
 233                                                 plic.ifc_external_irq[i].irq_frm_gateway(True);
 234                                         end
 235              endrule
 236           `else
 237              rule rl_connect_dma_interrupts_to_plic;
 238                  ff_gateway_queue[i].enq(0);
 239              endrule
 240           `endif
 241          end
 242                         */
 243          rule rl_connect_i2c0_to_plic;
 244                                 `ifdef I2C0
 245                                         if(i2c0.isint()==1'b1) begin
 246                                                 ff_gateway_queue[8].enq(1);
 247                                                 plic.ifc_external_irq[8].irq_frm_gateway(True);
 248                                         end
 249                                 `else
 250                                         ff_gateway_queue[8].enq(0);
 251             `endif
 252          endrule
 253
 254                         rule rl_connect_i2c1_to_plic;
 255                                 `ifdef I2C1
 256                                         if(i2c1.isint()==1'b1) begin
 257                                                 ff_gateway_queue[9].enq(1);
 258                                                 plic.ifc_external_irq[9].irq_frm_gateway(True);
 259                                         end
 260             `else
 261                                         ff_gateway_queue[9].enq(0);
 262             `endif
 263                         endrule
 264
 265          rule rl_connect_i2c0_timerint_to_plic;
 266                                 `ifdef I2C0
 267                                         if(i2c0.timerint()==1'b1) begin
 268                                                 ff_gateway_queue[10].enq(1);
 269                                                 plic.ifc_external_irq[10].irq_frm_gateway(True);
 270                                         end
 271             `else
 272                                         ff_gateway_queue[10].enq(0);
 273             `endif
 274                         endrule
 275
 276          rule rl_connect_i2c1_timerint_to_plic;
 277                                 `ifdef I2C1
 278                                         if(i2c1.timerint()==1'b1) begin
 279                                                 ff_gateway_queue[11].enq(1);
 280                                                 plic.ifc_external_irq[11].irq_frm_gateway(True);
 281                                         end
 282             `else
 283                                         ff_gateway_queue[11].enq(0);
 284             `endif
 285          endrule
 286
 287          rule rl_connect_i2c0_isber_to_plic;
 288                                 `ifdef I2C0
 289                                         if(i2c0.isber()==1'b1) begin
 290                                                 ff_gateway_queue[12].enq(1);
 291                                                 plic.ifc_external_irq[12].irq_frm_gateway(True);
 292                                         end
 293             `else
 294                                         ff_gateway_queue[12].enq(0);
 295             `endif
 296          endrule
 297
 298          rule rl_connect_i2c1_isber_to_plic;
 299                                 `ifdef I2C1
 300                                         if(i2c1.isber()==1'b1) begin
 301                                                 ff_gateway_queue[13].enq(1);
 302                                                 plic.ifc_external_irq[13].irq_frm_gateway(True);
 303                end
 304             `else
 305                                         ff_gateway_queue[13].enq(0);
 306             `endif
 307          endrule
 308
 309          for(Integer i = 14; i < 20; i=i+1) begin
 310                                 rule rl_connect_qspi0_to_plic;
 311                                         `ifdef QSPI0
 312                                                 if(qspi0.interrupts()[i-14]==1'b1) begin
 313                                                         ff_gateway_queue[i].enq(1);
 314                                                         plic.ifc_external_irq[i].irq_frm_gateway(True);
 315                                                 end
 316                `else
 317                                                 ff_gateway_queue[i].enq(0);
 318                `endif
 319             endrule
 320          end
 321
 322          for(Integer i = 20; i<26; i=i+1) begin
 323                                 rule rl_connect_qspi1_to_plic;
 324                                         `ifdef QSPI1
 325                                                 if(qspi1.interrupts()[i-20]==1'b1) begin
 326                                                         ff_gateway_queue[i].enq(1);
 327                                                         plic.ifc_external_irq[i].irq_frm_gateway(True);
 328                                                 end
 329                `else
 330                                                 ff_gateway_queue[i].enq(0);
 331                `endif
 332             endrule
 333                         end
 334
 335                         `ifdef UART0
 336                                 SyncBitIfc#(Bit#(1)) uart0_interrupt <-mkSyncBitToCC(uart_clock,uart_reset);
 337                                 rule synchronize_the_uart0_interrupt;
 338                                         uart0_interrupt.send(uart0.irq);
 339                                 endrule
 340                         `endif
 341                         rule rl_connect_uart_to_plic;
 342                                 `ifdef UART0
 343                                         if(uart0_interrupt.read==1'b1) begin
 344                                                 ff_gateway_queue[27].enq(1);
 345                                                 plic.ifc_external_irq[27].irq_frm_gateway(True);
 346                end
 347
 348             `else
 349                                         ff_gateway_queue[27].enq(0);
 350             `endif
 351          endrule
 352
 353                         for(Integer i = 28; i<`INTERRUPT_PINS; i=i+1) begin
 354                                 rule rl_raise_interrupts;
 355                                         if((i-28)<`IONum) begin //Peripheral interrupts
 356                                                 if(gpio.to_plic[i-28]==1'b1) begin
 357                                                         plic.ifc_external_irq[i].irq_frm_gateway(True);
 358                                                                 ff_gateway_queue[i].enq(1);
 359                   end
 360                                         end
 361                                 endrule
 362                         end
 363
 364          rule rl_completion_msg_from_plic;
 365                                 let id <- plic.intrpt_completion;
 366             interrupt_id <= id;
 367             `ifdef verbose $display("Dequeing the FIFO -- PLIC Interrupt Serviced id: %d",id); `endif
 368                         endrule
 369
 370          for(Integer i=0; i <`INTERRUPT_PINS; i=i+1) begin
 371                                 rule deq_gateway_queue;
 372                                         if(interrupt_id==fromInteger(i)) begin
 373                                                 ff_gateway_queue[i].deq;
 374                   `ifdef $display($time,"Dequeing the Interrupt request for ID: %d",i); `endif
 375                end
 376             endrule
 377          end
 378
 379
 380                 `endif
 381                         /*======================================================= */
 382
 383                 /* ===== interface definition =======*/
 384                 interface axi_slave=bridge.axi_slave;
 385                 `ifdef PLIC method intrpt_note = plic.intrpt_note; `endif
 386                 `ifdef CLINT
 387                         method msip_int=clint.msip_int;
 388                         method mtip_int=clint.mtip_int;
 389                         method mtime=clint.mtime;
 390                 `endif
 391                 `ifdef I2C0
 392                         method i2c0_isint=i2c0.isint;
 393                 `endif
 394                 `ifdef I2C1
 395                         method i2c1_isint=i2c1.isint;
 396                 `endif
 397                 `ifdef QSPI0 method     qspi0_isint=qspi0.interrupts[5]; `endif
 398                 `ifdef QSPI1 method     qspi1_isint=qspi1.interrupts[5]; `endif
 399                 `ifdef UART0 method uart0_intr=uart0.irq; `endif
 400                 interface SP_ios slow_ios;
 401                         `ifdef UART0
 402                                 interface uart0_coe=uart0.coe_rs232;
 403                         `endif
 404                         `ifdef UART1
 405                                 interface uart1_coe=uart1.coe_rs232;
 406                         `endif
 407                         `ifdef I2C0
 408                                 interface i2c0_out=i2c0.out;
 409                         `endif
 410                         `ifdef I2C1
 411                                 interface i2c1_out=i2c1.out;
 412                         `endif
 413                         `ifdef QSPI0
 414                                 interface qspi0_out = qspi0.out;
 415                         `endif
 416                         `ifdef QSPI1
 417                                 interface qspi1_out = qspi1.out;
 418                         `endif
 419                         `ifdef AXIEXP
 420                                 interface axiexp1_out=axiexp1.slave_out;
 421                                 interface axiexp1_in=axiexp1.slave_in;
 422                         `endif
 423       `ifdef PWM_AXI4Lite
 424         interface pwm_o = pwm_bus.pwm_io;
 425       `endif
 426                 endinterface
 427     // NEEL EDIT
 428     interface iocell_side=pinmux.iocell_side;
 429     interface pad_configa= gpioa.pad_config;
 430     method Action external_int(Bit#(32) in);
 431       wr_interrupt<= in;
 432     endmethod
 433     // NEEL EDIT OVER
 434                 /*===================================*/
 435         endmodule
 436 endpackage