src/bsv/bsv_lib/slow_peripherals_template.bsv

   1 package slow_peripherals;
   2         /*===== Project imports =====*/
   3         import defined_types::*;
   4         import AXI4_Lite_Fabric::*;
   5         import AXI4_Lite_Types::*;
   6         import AXI4_Fabric::*;
   7         import AXI4_Types::*;
   8         import Semi_FIFOF::*;
   9         import AXI4Lite_AXI4_Bridge::*;
  10         `include "instance_defines.bsv"
  11     /* ==== define the AXI Addresses ==== */
  12 {2}
  13     /* ==== define the number of slow peripheral irqs ==== */
  14 {11}
  15     /*====== AXI4 Lite slave declarations =======*/
  16
  17 {3}
  18         /*===========================*/
  19         /*=== package imports ===*/
  20         import Clocks::*;
  21         import GetPut::*;
  22         import ClientServer::*;
  23         import Connectable::*;
  24         import Vector::*;
  25         import FIFO::*;
  26         /*=======================*/
  27         /*===== Import the slow peripherals ====*/
  28 {0}
  29     `ifdef CLINT
  30         import clint::*;
  31     `endif
  32     `ifdef PLIC
  33         import plic             ::*;
  34     `endif
  35         `ifdef AXIEXP
  36                 import axiexpansion     ::*;
  37         `endif
  38         /*=====================================*/
  39
  40         /*===== interface declaration =====*/
  41         interface SP_dedicated_ios;
  42                 `ifdef AXIEXP
  43                         interface Get#(Bit#(67)) axiexp1_out;
  44                         interface Put#(Bit#(67)) axiexp1_in;
  45                 `endif
  46         endinterface
  47         interface Ifc_slow_peripherals;
  48                 interface AXI4_Slave_IFC#(`ADDR,`DATA,`USERSPACE) axi_slave;
  49                 interface SP_dedicated_ios slow_ios;
  50                 `ifdef CLINT
  51                         method Bit#(1) msip_int;
  52                         method Bit#(1) mtip_int;
  53                         method Bit#(`DATA) mtime;
  54                 `endif
  55                 `ifdef PLIC method ActionValue#(Tuple2#(Bool,Bool)) intrpt_note; `endif
  56         interface IOCellSide iocell_side; // mandatory interface
  57         `ifdef PLIC
  58 {1}
  59         `endif
  60         endinterface
  61         /*================================*/
  62
  63         function Tuple2#(Bool, Bit#(TLog#(Num_Slow_Slaves)))
  64                      fn_address_mapping (Bit#(`ADDR) addr);
  65         `ifdef CLINT
  66             if(addr>=`ClintBase && addr<=`ClintEnd)
  67                 return tuple2(True,fromInteger(valueOf(CLINT_slave_num)));
  68             else
  69         `endif
  70         `ifdef PLIC
  71             if(addr>=`PLICBase && addr<=`PLICEnd)
  72                 return tuple2(True,fromInteger(valueOf(Plic_slave_num)));
  73             else
  74         `endif
  75         `ifdef AXIEXP
  76             if(addr>=`AxiExp1Base && addr<=`AxiExp1End)
  77                 return tuple2(True,fromInteger(valueOf(AxiExp1_slave_num)));
  78             else
  79         `endif
  80 {4}
  81         return tuple2(False,?);
  82         endfunction
  83
  84         (*synthesize*)
  85         module mkslow_peripherals#(Clock fast_clock, Reset fast_reset,
  86                                Clock uart_clock, Reset uart_reset
  87                               `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif
  88                               )(Ifc_slow_peripherals);
  89                 Clock sp_clock <-exposeCurrentClock; // slow peripheral clock
  90                 Reset sp_reset <-exposeCurrentReset; // slow peripheral reset
  91
  92                 /*======= Module declarations for each peripheral =======*/
  93 {5}
  94                 `ifdef CLINT
  95                         Ifc_clint       clint <- mkclint();
  96                 `endif
  97                 `ifdef PLIC
  98                         Ifc_PLIC_AXI    plic <- mkplicperipheral();
  99             Wire#(Bit#(TLog#(`INTERRUPT_PINS))) interrupt_id <- mkWire();
 100             Vector#(`INTERRUPT_PINS, FIFO#(bit))
 101                             ff_gateway_queue <- replicateM(mkFIFO);
 102                 `endif
 103                 `ifdef AXIEXP
 104                         Ifc_AxiExpansion axiexp1 <- mkAxiExpansion();
 105                 `endif
 106         Ifc_pinmux pinmux <- mkpinmux; // mandatory
 107
 108                 /*=======================================================*/
 109
 110             AXI4_Lite_Fabric_IFC #(1, Num_Slow_Slaves, `ADDR, `DATA,`USERSPACE)
 111                 slow_fabric <- mkAXI4_Lite_Fabric(fn_address_mapping);
 112                 Ifc_AXI4Lite_AXI4_Bridge
 113                 bridge<-mkAXI4Lite_AXI4_Bridge(fast_clock,fast_reset);
 114
 115                 mkConnection (bridge.axi4_lite_master, slow_fabric.v_from_masters [0]);
 116                 /*======= Slave connections to AXI4Lite fabric =========*/
 117 {6}
 118                 `ifdef CLINT
 119                         mkConnection (slow_fabric.v_to_slaves
 120                     [fromInteger(valueOf(CLINT_slave_num))],
 121                     clint.axi4_slave);
 122                 `endif
 123                 `ifdef PLIC
 124                         mkConnection (slow_fabric.v_to_slaves
 125                     [fromInteger(valueOf(Plic_slave_num))],
 126                     plic.axi4_slave_plic); //
 127                 `endif
 128                 `ifdef AXIEXP
 129                 mkConnection (slow_fabric.v_to_slaves
 130                     [fromInteger(valueOf(AxiExp1_slave_num))],
 131                     axiexp1.axi_slave); //
 132                 `endif
 133
 134     /*========== pinmux connections ============*/
 135 {7}
 136 {8}
 137
 138     /*=================== PLIC Connections ==================== */
 139 `ifdef PLIC
 140 {10}
 141
 142     rule rl_completion_msg_from_plic;
 143           let id <- plic.intrpt_completion;
 144       interrupt_id <= id;
 145       `ifdef verbose
 146         $display("Dequeing the FIFO -- PLIC Interrupt Serviced id: %d",id);
 147        `endif
 148         endrule
 149
 150     for(Integer i=0; i <`INTERRUPT_PINS; i=i+1) begin
 151             rule deq_gateway_queue;
 152                     if(interrupt_id==fromInteger(i)) begin
 153                             ff_gateway_queue[i].deq;
 154           `ifdef verbose
 155             $display($time,"Dequeing the Interrupt request for ID: %d",i);
 156           `endif
 157         end
 158       endrule
 159     end
 160     /*TODO DMA interrupt need to be connected to the plic */
 161     for(Integer i=1; i<8; i=i+1) begin
 162       rule rl_connect_dma_interrupts_to_plic;
 163        `ifdef DMA
 164             if(dma.interrupt_to_processor[i-1]==1'b1) begin
 165                 ff_gateway_queue[i].enq(1);
 166                 plic.ifc_external_irq[i].irq_frm_gateway(True);
 167             end
 168         `else
 169             ff_gateway_queue[i].enq(0);
 170         `endif
 171       endrule
 172     end
 173
 174 `endif // end PLIC
 175         /*======================================================= */
 176
 177                 /* ===== interface definition =======*/
 178                 interface axi_slave=bridge.axi_slave;
 179                 `ifdef PLIC method intrpt_note = plic.intrpt_note; `endif
 180                 `ifdef CLINT
 181                         method msip_int=clint.msip_int;
 182                         method mtip_int=clint.mtip_int;
 183                         method mtime=clint.mtime;
 184                 `endif
 185 `ifdef PLIC
 186 {12}
 187 `endif // end PLIC
 188                 interface SP_dedicated_ios slow_ios;
 189         /* template for dedicated peripherals
 190                         `ifdef UART0
 191                                 interface uart0_coe=uart0.coe_rs232;
 192                         `endif
 193                         `ifdef UART1
 194                                 interface uart1_coe=uart1.coe_rs232;
 195                         `endif
 196                         `ifdef I2C0
 197                                 interface i2c0_out=i2c0.out;
 198                         `endif
 199                         `ifdef I2C1
 200                                 interface i2c1_out=i2c1.out;
 201                         `endif
 202                         `ifdef QSPI0
 203                                 interface qspi0_out = qspi0.out;
 204                         `endif
 205                         `ifdef QSPI1
 206                                 interface qspi1_out = qspi1.out;
 207                         `endif
 208                         `ifdef AXIEXP
 209                                 interface axiexp1_out=axiexp1.slave_out;
 210                                 interface axiexp1_in=axiexp1.slave_in;
 211                         `endif
 212             `ifdef PWM_AXI4Lite
 213                 interface pwm_o = pwm_bus.pwm_io;
 214             `endif
 215        */
 216                 endinterface
 217         interface iocell_side=pinmux.iocell_side;
 218 {9}
 219 {13}
 220                 /*===================================*/
 221         endmodule
 222 endpackage