src/bsv/bsv_lib/slow_peripherals_template.bsv

   1 package slow_peripherals;
   2         /*===== Project imports =====*/
   3         import defined_types::*;
   4         import AXI4_Lite_Fabric::*;
   5         import AXI4_Lite_Types::*;
   6         import AXI4_Fabric::*;
   7         import AXI4_Types::*;
   8         import Semi_FIFOF::*;
   9         import AXI4Lite_AXI4_Bridge::*;
  10         `include "instance_defines.bsv"
  11     /* ==== define the AXI Addresses ==== */
  12 {2}
  13     /*====== AXI4 Lite slave declarations =======*/
  14
  15 {3}
  16         /*===========================*/
  17         /*=== package imports ===*/
  18         import Clocks::*;
  19         import GetPut::*;
  20         import ClientServer::*;
  21         import Connectable::*;
  22         import Vector::*;
  23         import FIFO::*;
  24         /*=======================*/
  25         /*===== Import the slow peripherals ====*/
  26 {0}
  27     `ifdef CLINT
  28         import clint::*;
  29     `endif
  30     `ifdef PLIC
  31         import plic             ::*;
  32     `endif
  33         `ifdef AXIEXP
  34                 import axiexpansion     ::*;
  35         `endif
  36         /*=====================================*/
  37
  38         /*===== interface declaration =====*/
  39         interface SP_ios;
  40 {1}
  41                 `ifdef AXIEXP
  42                         interface Get#(Bit#(67)) axiexp1_out;
  43                         interface Put#(Bit#(67)) axiexp1_in;
  44                 `endif
  45         endinterface
  46         interface Ifc_slow_peripherals;
  47                 interface AXI4_Slave_IFC#(`PADDR,`Reg_width,`USERSPACE) axi_slave;
  48                 interface SP_ios slow_ios;
  49     method Action external_int(Bit#(32) in);
  50                 `ifdef CLINT
  51                         method Bit#(1) msip_int;
  52                         method Bit#(1) mtip_int;
  53                         method Bit#(`Reg_width) mtime;
  54                 `endif
  55                 `ifdef PLIC method ActionValue#(Tuple2#(Bool,Bool)) intrpt_note; `endif
  56     interface IOCellSide iocell_side; // mandatory interface
  57         endinterface
  58         /*================================*/
  59
  60         function Tuple2#(Bool, Bit#(TLog#(Num_Slow_Slaves)))
  61                      fn_address_mapping (Bit#(`PADDR) addr);
  62                 `ifdef CLINT
  63                         if(addr>=`ClintBase && addr<=`ClintEnd)
  64                                 return tuple2(True,fromInteger(valueOf(CLINT_slave_num)));
  65                         else
  66                 `endif
  67                 `ifdef PLIC
  68                         if(addr>=`PLICBase && addr<=`PLICEnd)
  69                                 return tuple2(True,fromInteger(valueOf(Plic_slave_num)));
  70                         else
  71                 `endif
  72                 `ifdef AXIEXP
  73                         if(addr>=`AxiExp1Base && addr<=`AxiExp1End)
  74                                 return tuple2(True,fromInteger(valueOf(AxiExp1_slave_num)));
  75                         else
  76                 `endif
  77 {4}
  78                         return tuple2(False,?);
  79         endfunction
  80
  81         (*synthesize*)
  82         module mkslow_peripherals#(Clock fast_clock, Reset fast_reset,
  83                                Clock uart_clock, Reset uart_reset
  84   `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif
  85                               )(Ifc_slow_peripherals);
  86                 Clock sp_clock <-exposeCurrentClock; // slow peripheral clock
  87                 Reset sp_reset <-exposeCurrentReset; // slow peripheral reset
  88
  89                 /*======= Module declarations for each peripheral =======*/
  90 {5}
  91                 `ifdef CLINT
  92                         Ifc_clint                               clint                           <- mkclint();
  93                 `endif
  94                 `ifdef PLIC
  95                         Ifc_PLIC_AXI    plic <- mkplicperipheral();
  96          Wire#(Bit#(TLog#(`INTERRUPT_PINS))) interrupt_id <- mkWire();
  97                           Vector#(32, FIFO#(bit)) ff_gateway_queue <- replicateM(mkFIFO);
  98                 `endif
  99                 `ifdef AXIEXP
 100                         Ifc_AxiExpansion                axiexp1                 <- mkAxiExpansion();
 101                 `endif
 102     Ifc_pinmux pinmux <- mkpinmux; // mandatory
 103     Wire#(Bit#(32)) wr_interrupt <- mkWire();
 104                 /*=======================================================*/
 105
 106         AXI4_Lite_Fabric_IFC #(1, Num_Slow_Slaves, `PADDR, `Reg_width,`USERSPACE)
 107             slow_fabric <- mkAXI4_Lite_Fabric(fn_address_mapping);
 108                 Ifc_AXI4Lite_AXI4_Bridge
 109             bridge<-mkAXI4Lite_AXI4_Bridge(fast_clock,fast_reset);
 110
 111                 mkConnection (bridge.axi4_lite_master,  slow_fabric.v_from_masters [0]);
 112                 /*======= Slave connections to AXI4Lite fabric =========*/
 113 {6}
 114                 `ifdef CLINT
 115                         mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(CLINT_slave_num))],
 116                     clint.axi4_slave);
 117                 `endif
 118                 `ifdef PLIC
 119                         mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(Plic_slave_num))],
 120                     plic.axi4_slave_plic); //
 121                 `endif
 122                 `ifdef QSPI0
 123                         mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(Qspi0_slave_num))],
 124                     qspi0.slave);
 125                 `endif
 126                 `ifdef QSPI1
 127                         mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(Qspi1_slave_num))],
 128                     qspi1.slave);
 129                 `endif
 130                 `ifdef AXIEXP
 131                 mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(AxiExp1_slave_num))],
 132                     axiexp1.axi_slave); //
 133                 `endif
 134     `ifdef PWM_AXI4Lite
 135       mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(Pwm_slave_num))],
 136                     pwm_bus.axi4_slave);
 137     `endif
 138
 139     // NEEL EDIT
 140     mkConnection (slow_fabric.
 141                   v_to_slaves[fromInteger(valueOf(Muxa_slave_num))],
 142                   muxa.axi_slave);
 143     mkConnection (slow_fabric.
 144                   v_to_slaves[fromInteger(valueOf(Gpioa_slave_num))],
 145                   gpioa.axi_slave);
 146     rule connect_select_lines_pinmux;// mandatory
 147       pinmux.mux_lines.cell0_mux(muxa.mux_config.mux[0]);
 148       pinmux.mux_lines.cell1_mux(muxa.mux_config.mux[1]);
 149       pinmux.mux_lines.cell2_mux(muxa.mux_config.mux[2]);
 150     endrule
 151     rule connect_i2c0_scl;
 152       pinmux.peripheral_side.twi_scl_out(i2c0.out.scl_out);
 153       pinmux.peripheral_side.twi_scl_outen(pack(i2c0.out.scl_out_en));
 154     endrule
 155     rule connect_i2c0_scl_in;
 156       i2c0.out.scl_in(pinmux.peripheral_side.twi_scl_in);
 157     endrule
 158     rule connect_i2c0_sda;
 159       pinmux.peripheral_side.twi_sda_out(i2c0.out.sda_out);
 160       pinmux.peripheral_side.twi_sda_outen(pack(i2c0.out.sda_out_en));
 161     endrule
 162     rule connect_i2c0_sda_in;
 163       i2c0.out.sda_in(pinmux.peripheral_side.twi_sda_in);
 164     endrule
 165     rule connect_uart1tx;
 166       pinmux.peripheral_side.uart_tx(uart1.coe_rs232.sout);
 167     endrule
 168     rule connect_uart1rx;
 169       uart1.coe_rs232.sin(pinmux.peripheral_side.uart_rx);
 170     endrule
 171     rule connect_gpioa;
 172       pinmux.peripheral_side.gpioa_a0_out(gpioa.func.gpio_out[0]);
 173       pinmux.peripheral_side.gpioa_a0_outen(gpioa.func.gpio_out_en[0]);
 174       pinmux.peripheral_side.gpioa_a1_out(gpioa.func.gpio_out[1]);
 175       pinmux.peripheral_side.gpioa_a1_outen(gpioa.func.gpio_out_en[1]);
 176       pinmux.peripheral_side.gpioa_a2_out(gpioa.func.gpio_out[2]);
 177       pinmux.peripheral_side.gpioa_a2_outen(gpioa.func.gpio_out_en[2]);
 178                 Vector#(3,Bit#(1)) temp;
 179                 temp[0]=pinmux.peripheral_side.gpioa_a0_in;
 180                 temp[1]=pinmux.peripheral_side.gpioa_a1_in;
 181                 temp[2]=pinmux.peripheral_side.gpioa_a2_in;
 182       gpioa.func.gpio_in(temp);
 183     endrule
 184     for(Integer i=0;i<32;i=i+ 1)begin
 185       rule connect_int_to_plic(wr_interrupt[i]==1);
 186                                 ff_gateway_queue[i].enq(1);
 187                                 plic.ifc_external_irq[i].irq_frm_gateway(True);
 188       endrule
 189     end
 190     rule rl_completion_msg_from_plic;
 191                   let id <- plic.intrpt_completion;
 192       interrupt_id <= id;
 193       `ifdef verbose $display("Dequeing the FIFO -- PLIC Interrupt Serviced id: %d",id); `endif
 194                 endrule
 195
 196     for(Integer i=0; i <32; i=i+1) begin
 197             rule deq_gateway_queue;
 198                     if(interrupt_id==fromInteger(i)) begin
 199                             ff_gateway_queue[i].deq;
 200           `ifdef $display($time,"Dequeing the Interrupt request for ID: %d",i); `endif
 201         end
 202       endrule
 203     end
 204     /* for connectin inputs from pinmux as itnerrupts
 205       rule connect_pinmux_eint;
 206         wr_interrupt<= pinmux.peripheral_side.eint_input;
 207       endrule
 208     */
 209     // NEEL EDIT OVER
 210                 /*=======================================================*/
 211                 /*=================== PLIC Connections ==================== */
 212                 `ifdef PLIC_main
 213                         /*TODO DMA interrupt need to be connected to the plic
 214                         for(Integer i=1; i<8; i=i+1) begin
 215          `ifdef DMA
 216              rule rl_connect_dma_interrupts_to_plic;
 217                                         if(dma.interrupt_to_processor[i-1]==1'b1) begin
 218                                                 ff_gateway_queue[i].enq(1);
 219                                                 plic.ifc_external_irq[i].irq_frm_gateway(True);
 220                                         end
 221              endrule
 222           `else
 223              rule rl_connect_dma_interrupts_to_plic;
 224                  ff_gateway_queue[i].enq(0);
 225              endrule
 226           `endif
 227          end
 228                         */
 229          rule rl_connect_i2c0_to_plic;
 230                                 `ifdef I2C0
 231                                         if(i2c0.isint()==1'b1) begin
 232                                                 ff_gateway_queue[8].enq(1);
 233                                                 plic.ifc_external_irq[8].irq_frm_gateway(True);
 234                                         end
 235                                 `else
 236                                         ff_gateway_queue[8].enq(0);
 237             `endif
 238          endrule
 239
 240                         rule rl_connect_i2c1_to_plic;
 241                                 `ifdef I2C1
 242                                         if(i2c1.isint()==1'b1) begin
 243                                                 ff_gateway_queue[9].enq(1);
 244                                                 plic.ifc_external_irq[9].irq_frm_gateway(True);
 245                                         end
 246             `else
 247                                         ff_gateway_queue[9].enq(0);
 248             `endif
 249                         endrule
 250
 251          rule rl_connect_i2c0_timerint_to_plic;
 252                                 `ifdef I2C0
 253                                         if(i2c0.timerint()==1'b1) begin
 254                                                 ff_gateway_queue[10].enq(1);
 255                                                 plic.ifc_external_irq[10].irq_frm_gateway(True);
 256                                         end
 257             `else
 258                                         ff_gateway_queue[10].enq(0);
 259             `endif
 260                         endrule
 261
 262          rule rl_connect_i2c1_timerint_to_plic;
 263                                 `ifdef I2C1
 264                                         if(i2c1.timerint()==1'b1) begin
 265                                                 ff_gateway_queue[11].enq(1);
 266                                                 plic.ifc_external_irq[11].irq_frm_gateway(True);
 267                                         end
 268             `else
 269                                         ff_gateway_queue[11].enq(0);
 270             `endif
 271          endrule
 272
 273          rule rl_connect_i2c0_isber_to_plic;
 274                                 `ifdef I2C0
 275                                         if(i2c0.isber()==1'b1) begin
 276                                                 ff_gateway_queue[12].enq(1);
 277                                                 plic.ifc_external_irq[12].irq_frm_gateway(True);
 278                                         end
 279             `else
 280                                         ff_gateway_queue[12].enq(0);
 281             `endif
 282          endrule
 283
 284          rule rl_connect_i2c1_isber_to_plic;
 285                                 `ifdef I2C1
 286                                         if(i2c1.isber()==1'b1) begin
 287                                                 ff_gateway_queue[13].enq(1);
 288                                                 plic.ifc_external_irq[13].irq_frm_gateway(True);
 289                end
 290             `else
 291                                         ff_gateway_queue[13].enq(0);
 292             `endif
 293          endrule
 294
 295          for(Integer i = 14; i < 20; i=i+1) begin
 296                                 rule rl_connect_qspi0_to_plic;
 297                                         `ifdef QSPI0
 298                                                 if(qspi0.interrupts()[i-14]==1'b1) begin
 299                                                         ff_gateway_queue[i].enq(1);
 300                                                         plic.ifc_external_irq[i].irq_frm_gateway(True);
 301                                                 end
 302                `else
 303                                                 ff_gateway_queue[i].enq(0);
 304                `endif
 305             endrule
 306          end
 307
 308          for(Integer i = 20; i<26; i=i+1) begin
 309                                 rule rl_connect_qspi1_to_plic;
 310                                         `ifdef QSPI1
 311                                                 if(qspi1.interrupts()[i-20]==1'b1) begin
 312                                                         ff_gateway_queue[i].enq(1);
 313                                                         plic.ifc_external_irq[i].irq_frm_gateway(True);
 314                                                 end
 315                `else
 316                                                 ff_gateway_queue[i].enq(0);
 317                `endif
 318             endrule
 319                         end
 320
 321                         `ifdef UART0
 322                                 SyncBitIfc#(Bit#(1)) uart0_interrupt <-mkSyncBitToCC(uart_clock,uart_reset);
 323                                 rule synchronize_the_uart0_interrupt;
 324                                         uart0_interrupt.send(uart0.irq);
 325                                 endrule
 326                         `endif
 327                         rule rl_connect_uart_to_plic;
 328                                 `ifdef UART0
 329                                         if(uart0_interrupt.read==1'b1) begin
 330                                                 ff_gateway_queue[27].enq(1);
 331                                                 plic.ifc_external_irq[27].irq_frm_gateway(True);
 332                end
 333
 334             `else
 335                                         ff_gateway_queue[27].enq(0);
 336             `endif
 337          endrule
 338
 339                         for(Integer i = 28; i<`INTERRUPT_PINS; i=i+1) begin
 340                                 rule rl_raise_interrupts;
 341                                         if((i-28)<`IONum) begin //Peripheral interrupts
 342                                                 if(gpio.to_plic[i-28]==1'b1) begin
 343                                                         plic.ifc_external_irq[i].irq_frm_gateway(True);
 344                                                                 ff_gateway_queue[i].enq(1);
 345                   end
 346                                         end
 347                                 endrule
 348                         end
 349
 350          rule rl_completion_msg_from_plic;
 351                                 let id <- plic.intrpt_completion;
 352             interrupt_id <= id;
 353             `ifdef verbose $display("Dequeing the FIFO -- PLIC Interrupt Serviced id: %d",id); `endif
 354                         endrule
 355
 356          for(Integer i=0; i <`INTERRUPT_PINS; i=i+1) begin
 357                                 rule deq_gateway_queue;
 358                                         if(interrupt_id==fromInteger(i)) begin
 359                                                 ff_gateway_queue[i].deq;
 360                   `ifdef $display($time,"Dequeing the Interrupt request for ID: %d",i); `endif
 361                end
 362             endrule
 363          end
 364
 365
 366                 `endif
 367                         /*======================================================= */
 368
 369                 /* ===== interface definition =======*/
 370                 interface axi_slave=bridge.axi_slave;
 371                 `ifdef PLIC method intrpt_note = plic.intrpt_note; `endif
 372                 `ifdef CLINT
 373                         method msip_int=clint.msip_int;
 374                         method mtip_int=clint.mtip_int;
 375                         method mtime=clint.mtime;
 376                 `endif
 377                 `ifdef I2C0
 378                         method i2c0_isint=i2c0.isint;
 379                 `endif
 380                 `ifdef I2C1
 381                         method i2c1_isint=i2c1.isint;
 382                 `endif
 383                 `ifdef QSPI0 method     qspi0_isint=qspi0.interrupts[5]; `endif
 384                 `ifdef QSPI1 method     qspi1_isint=qspi1.interrupts[5]; `endif
 385                 `ifdef UART0 method uart0_intr=uart0.irq; `endif
 386                 interface SP_ios slow_ios;
 387                         `ifdef UART0
 388                                 interface uart0_coe=uart0.coe_rs232;
 389                         `endif
 390                         `ifdef UART1
 391                                 interface uart1_coe=uart1.coe_rs232;
 392                         `endif
 393                         `ifdef I2C0
 394                                 interface i2c0_out=i2c0.out;
 395                         `endif
 396                         `ifdef I2C1
 397                                 interface i2c1_out=i2c1.out;
 398                         `endif
 399                         `ifdef QSPI0
 400                                 interface qspi0_out = qspi0.out;
 401                         `endif
 402                         `ifdef QSPI1
 403                                 interface qspi1_out = qspi1.out;
 404                         `endif
 405                         `ifdef AXIEXP
 406                                 interface axiexp1_out=axiexp1.slave_out;
 407                                 interface axiexp1_in=axiexp1.slave_in;
 408                         `endif
 409       `ifdef PWM_AXI4Lite
 410         interface pwm_o = pwm_bus.pwm_io;
 411       `endif
 412                 endinterface
 413     // NEEL EDIT
 414     interface iocell_side=pinmux.iocell_side;
 415     interface pad_configa= gpioa.pad_config;
 416     method Action external_int(Bit#(32) in);
 417       wr_interrupt<= in;
 418     endmethod
 419     // NEEL EDIT OVER
 420                 /*===================================*/
 421         endmodule
 422 endpackage