src/bsv/bsv_lib/soc_template.bsv

   1 /*
   2 Copyright (c) 2013, IIT Madras
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without
   6 modification, are permitted provided that the following conditions
   7 are met:
   8
   9 *  Redistributions of source code must retain the above copyright notice,
  10    this list of conditions and the following disclaimer.
  11 *  Redistributions in binary form must reproduce the above copyright
  12    notice, this list of conditions and the following disclaimer in the
  13    documentation and/or other materials provided with the distribution.
  14 *  Neither the name of IIT Madras  nor the names of its contributors
  15    may be used to endorse or promote products derived from this software
  16    without specific prior written permission.
  17
  18 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  19 "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  20 LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  21 A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  22 HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  23 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
  24 TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  25 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  26 LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  27 NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  28 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29 -------------------------------------------------------------------
  30 */
  31 package socgen;
  32     /*====== Package imports === */
  33     import FIFO::*;
  34     import FIFOF::*;
  35     import SpecialFIFOs::*;
  36     import GetPut::*;
  37     import ClientServer::*;
  38     import Vector::*;
  39     import Connectable::*;
  40     import Clocks::*;
  41
  42     /*=== Project imports === */
  43     import ifc_sync:: *;
  44     import ConcatReg::*;
  45     import AXI4_Types::*;
  46     import AXI4_Fabric::*;
  47     import defined_types::*;
  48     import MemoryMap             :: *;
  49     import slow_peripherals::*;
  50     import fast_memory_map::*;
  51     import slow_memory_map::*;
  52 `ifdef DEBUG
  53     `include "defines.bsv"
  54 `endif
  55     `include "instance_defines.bsv"
  56     `include "core_parameters.bsv"
  57 {8}
  58
  59     `ifdef DMA
  60         import DMA                               :: *;
  61     `endif
  62     `ifdef BOOTROM
  63         import BootRom                  ::*;
  64     `endif
  65     `ifdef SDRAM
  66         import sdr_top                   :: *;
  67     `endif
  68     `ifdef BRAM
  69         import Memory_AXI4      ::*;
  70     `endif
  71     `ifdef TCMemory
  72         import TCM::*;
  73     `endif
  74     `ifdef Debug
  75         import DebugModule::*;
  76     `else
  77         import core::*;
  78     `endif
  79     `ifdef  VME
  80         import vme_top ::*;
  81     `endif
  82
  83     `ifdef VME
  84         import vme_master::*;
  85     `endif
  86     `ifdef FlexBus
  87         import FlexBus_Types::*;
  88     `endif
  89 {0}
  90
  91     /*========================= */
  92     interface Ifc_Soc;
  93         interface SP_dedicated_ios slow_ios;
  94         (*always_ready,always_enabled*)
  95         method Action boot_sequence(Bit#(1) bootseq);
  96
  97         `ifdef SDRAM
  98             (*always_ready*) interface Ifc_sdram_out sdram_out;
  99         `endif
 100         `ifdef DDR
 101             (*prefix="M_AXI"*) interface
 102                    AXI4_Master_IFC#(`PADDR, `DATA, `USERSPACE) master;
 103         `endif
 104         `ifdef HYPER
 105              (*always_ready,always_enabled*)
 106              interface Ifc_flash ifc_flash;
 107         `endif
 108         /*=============================================== */
 109         `ifdef VME
 110              interface Vme_out  proc_ifc;
 111              interface Data_bus_inf proc_dbus;
 112         `endif
 113 {1}
 114     endinterface
 115
 116     //============ mkSoc module =================
 117
 118     (*synthesize*)
 119     module mkSoc #(Bit#(`VADDR) reset_vector,
 120                  Clock slow_clock, Reset slow_reset, Clock uart_clock,
 121                  Reset uart_reset, Clock clk0, Clock tck, Reset trst
 122                  `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif )(Ifc_Soc);
 123         Clock core_clock <-exposeCurrentClock; // slow peripheral clock
 124         Reset core_reset <-exposeCurrentReset; // slow peripheral reset
 125 {2}
 126         `ifdef Debug
 127             Ifc_DebugModule core<-mkDebugModule(reset_vector);
 128         `else
 129             Ifc_core_AXI4 core <-mkcore_AXI4(reset_vector);
 130         `endif
 131         `ifdef BOOTROM
 132             BootRom_IFC bootrom <-mkBootRom;
 133         `endif
 134         `ifdef SDRAM
 135             Ifc_sdr_slave sdram<- mksdr_axi4_slave(clk0);
 136         `endif
 137         `ifdef BRAM
 138             Memory_IFC#(`SDRAMMemBase,`Addr_space)main_memory <-
 139                         mkMemory("code.mem.MSB","code.mem.LSB","MainMEM");
 140         `endif
 141         `ifdef TCMemory
 142             Ifc_TCM                                     tcm                             <- mkTCM;
 143         `endif
 144         `ifdef DMA
 145             DmaC#(7,`NUM_DMACHANNELS) dma       <- mkDMA();
 146         `endif
 147             `ifdef VME
 148             Ifc_vme_top             vme             <-mkvme_top();
 149             `endif
 150         Ifc_slow_peripherals slow_peripherals <-mkslow_peripherals(
 151                           core_clock, core_reset,
 152                           uart_clock, uart_reset,
 153                           clocked_by slow_clock, reset_by slow_reset
 154                           `ifdef PWM_AXI4Lite , ext_pwm_clock `endif );
 155
 156         // clock sync mkConnections
 157 {12}
 158
 159         // Fabric
 160         AXI4_Fabric_IFC #(Num_Masters, Num_Fast_Slaves,
 161                           `PADDR, `DATA,`USERSPACE)
 162                         fabric <- mkAXI4_Fabric(fn_addr_to_slave_num);
 163
 164         // Connect traffic generators to fabric
 165         mkConnection (core.dmem_master,fabric.v_from_masters
 166                               [fromInteger(valueOf(Dmem_master_num))]);
 167         mkConnection (core.imem_master, fabric.v_from_masters
 168                               [fromInteger(valueOf(Imem_master_num))]);
 169         `ifdef Debug
 170             mkConnection (core.debug_master, fabric.v_from_masters
 171                               [fromInteger(valueOf(Debug_master_num))]);
 172         `endif
 173         `ifdef DMA
 174          mkConnection (dma.mmu, fabric.v_from_masters
 175                               [fromInteger(valueOf(DMA_master_num))]);
 176         `endif
 177
 178
 179         // Connect fabric to memory slaves
 180             `ifdef Debug
 181                 mkConnection (fabric.v_to_slaves
 182                               [fromInteger(valueOf(Debug_slave_num))],
 183                               core.debug_slave);
 184             `endif
 185             `ifdef SDRAM
 186                 mkConnection (fabric.v_to_slaves
 187                               [fromInteger(valueOf(Sdram_slave_num))],
 188                               sdram.axi4_slave_sdram); //
 189             mkConnection (fabric.v_to_slaves
 190                               [fromInteger(valueOf(Sdram_cfg_slave_num))],
 191                               sdram.axi4_slave_cntrl_reg); //
 192       `endif
 193       `ifdef BRAM
 194                 mkConnection(fabric.v_to_slaves
 195                               [fromInteger(valueOf(Sdram_slave_num))],
 196                               main_memory.axi_slave);
 197             `endif
 198             `ifdef BOOTROM
 199                 mkConnection (fabric.v_to_slaves
 200                               [fromInteger(valueOf(BootRom_slave_num))],
 201                               bootrom.axi_slave);
 202             `endif
 203             `ifdef DMA
 204             mkConnection (fabric.v_to_slaves
 205                               [fromInteger(valueOf(Dma_slave_num))],
 206                               dma.cfg); //DMA slave
 207             `endif
 208             `ifdef TCMemory
 209                 mkConnection (fabric.v_to_slaves
 210                               [fromInteger(valueOf(TCM_slave_num))],
 211                               tcm.axi_slave);
 212             `endif
 213             mkConnection(fabric.v_to_slaves
 214                               [fromInteger(valueOf(SlowPeripheral_slave_num))],
 215                               slow_peripherals.axi_slave);
 216             `ifdef VME
 217                 mkConnection (fabric.v_to_slaves
 218                               [fromInteger(valueOf(VME_slave_num))],
 219                               vme.slave_axi_vme);
 220             `endif
 221
 222 //          pin connections
 223 {9}
 224
 225             // fabric connections
 226 {5}
 227
 228             `ifdef DMA
 229             // rule to connect all interrupt lines to the DMA
 230             // All the interrupt lines to DMA are active
 231             // HIGH. For peripherals that are not connected,
 232             // or those which do not
 233             // generate an interrupt (like TCM), drive a constant 1
 234             // on the corresponding interrupt line.
 235 {7}
 236             `endif
 237
 238
 239         /*==== Synchornization between the JTAG and the Debug Module ===== */
 240         `ifdef Debug
 241             SyncFIFOIfc#(Bit#(40)) sync_request_to_dm <-
 242                                         mkSyncFIFOToCC(1,tck,trst);
 243             SyncFIFOIfc#(Bit#(34)) sync_response_from_dm <-
 244                                         mkSyncFIFOFromCC(1,tck);
 245             rule connect_tap_request_to_syncfifo;
 246                 let x<-tap.request_to_dm;
 247                 sync_request_to_dm.enq(x);
 248             endrule
 249             rule read_synced_request_to_dm;
 250                 sync_request_to_dm.deq;
 251                 core.request_from_dtm(sync_request_to_dm.first);
 252             endrule
 253
 254             rule connect_debug_response_to_syncfifo;
 255                 let x<-core.response_to_dtm;
 256                 sync_response_from_dm.enq(x);
 257             endrule
 258             rule read_synced_response_from_dm;
 259                 sync_response_from_dm.deq;
 260                 tap.response_from_dm(sync_response_from_dm.first);
 261             endrule
 262         `endif
 263         /*============================================================ */
 264
 265         `ifdef FlexBus
 266             //rule drive_flexbus_inputs;
 267                //flexbus.flexbus_side.m_TAn(1'b1);
 268                //flexbus.flexbus_side.m_din(32'haaaaaaaa);
 269             //endrule
 270          `endif
 271
 272         `ifdef CLINT
 273             SyncBitIfc#(Bit#(1)) clint_mtip_int <-
 274                                         mkSyncBitToCC(slow_clock,slow_reset);
 275             SyncBitIfc#(Bit#(1)) clint_msip_int <-
 276                                         mkSyncBitToCC(slow_clock,slow_reset);
 277             Reg#(Bit#(`DATA)) clint_mtime_value <-
 278                                         mkSyncRegToCC(0,slow_clock,slow_reset);
 279             rule synchronize_clint_data;
 280                 clint_mtip_int.send(slow_peripherals.mtip_int);
 281                 clint_msip_int.send(slow_peripherals.msip_int);
 282                 clint_mtime_value<=slow_peripherals.mtime;
 283             endrule
 284             rule connect_msip_mtip_from_clint;
 285                 core.clint_msip(clint_msip_int.read);
 286                 core.clint_mtip(clint_mtip_int.read);
 287             core.clint_mtime(clint_mtime_value);
 288             endrule
 289         `endif
 290         `ifdef PLIC
 291             Reg#(Tuple2#(Bool,Bool)) plic_interrupt_note <-
 292                                         mkSyncRegToCC(tuple2(False,False),
 293                                                       slow_clock,slow_reset);
 294             rule synchronize_interrupts;
 295                 let note <- slow_peripherals.intrpt_note;
 296                 plic_interrupt_note<=note;
 297             endrule
 298             rule rl_send_external_interrupt_to_csr;
 299                 core.set_external_interrupt(plic_interrupt_note);
 300             endrule
 301         `endif
 302
 303         `ifdef VME
 304             interface  proc_ifc = vme.proc_ifc;
 305             interface   proc_dbus = vme.proc_dbus;
 306         `endif
 307          method Action boot_sequence(Bit#(1) bootseq) =
 308                             core.boot_sequence(bootseq);
 309         `ifdef SDRAM
 310             interface sdram_out=sdram.ifc_sdram_out;
 311         `endif
 312         `ifdef DDR
 313           interface master=fabric.v_to_slaves
 314                                 [fromInteger(valueOf(Sdram_slave_num))];
 315         `endif
 316         interface slow_ios = slow_peripherals.slow_ios;
 317         interface iocell_side = slow_peripherals.iocell_side;
 318
 319 {6}
 320     endmodule
 321 endpackage