2 Copyright (c) 2013, IIT Madras
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16 without specific prior written permission.
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19 "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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24 TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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27 NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 -------------------------------------------------------------------
32 /*====== Package imports === */
35 import SpecialFIFOs::*;
37 import ClientServer::*;
39 import Connectable::*;
41 /*========================== */
42 /*=== Project imports === */
45 import AXI4_Fabric::*;
46 import defined_types::*;
47 import MemoryMap :: *;
48 import slow_peripherals::*;
49 `include "defines.bsv"
50 `include "instance_defines.bsv"
52 /*====== AXI4 slave declarations =======*/
54 /*====== AXI4 Master declarations =======*/
68 import Memory_AXI4 ::*;
75 import DebugModule::*;
87 import FlexBus_Types::*;
91 /*========================= */
93 interface SP_ios slow_ios;
94 (*always_ready,always_enabled*)
95 method Action boot_sequence(Bit#(1) bootseq);
98 (*always_ready*) interface Ifc_sdram_out sdram_out;
101 (*prefix="M_AXI"*) interface
102 AXI4_Master_IFC#(`PADDR, `Reg_width, `USERSPACE) master;
105 (*always_ready,always_enabled*)
106 interface Ifc_flash ifc_flash;
108 /*=============================================== */
110 interface Vme_out proc_ifc;
111 interface Data_bus_inf proc_dbus;
114 interface FlexBus_Master_IFC flexbus_out;
120 module mkSoc #(Bit#(`VADDR) reset_vector,
121 Clock slow_clock, Reset slow_reset, Clock uart_clock,
122 Reset uart_reset, Clock clk0, Clock tck, Reset trst
123 `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif )(Ifc_Soc);
124 Clock core_clock <-exposeCurrentClock; // slow peripheral clock
125 Reset core_reset <-exposeCurrentReset; // slow peripheral reset
128 Ifc_DebugModule core<-mkDebugModule(reset_vector);
130 Ifc_core_AXI4 core <-mkcore_AXI4(reset_vector);
133 BootRom_IFC bootrom <-mkBootRom;
136 Ifc_sdr_slave sdram<- mksdr_axi4_slave(clk0);
139 Memory_IFC#(`SDRAMMemBase,`Addr_space)main_memory <-
140 mkMemory("code.mem.MSB","code.mem.LSB","MainMEM");
143 Ifc_TCM tcm <- mkTCM;
146 DmaC#(7,`NUM_DMACHANNELS) dma <- mkDMA();
149 Ifc_vme_top vme <-mkvme_top();
152 AXI4_Slave_to_FlexBus_Master_Xactor_IFC #(32, 64,0)
153 flexbus <- mkAXI4_Slave_to_FlexBus_Master_Xactor;
155 Ifc_slow_peripherals slow_peripherals <-mkslow_peripherals(
156 core_clock, core_reset, uart_clock,
157 uart_reset, clocked_by slow_clock ,
159 `ifdef PWM_AXI4Lite , ext_pwm_clock `endif );
162 AXI4_Fabric_IFC #(Num_Masters, Num_Slaves,
163 `PADDR, `Reg_width,`USERSPACE)
164 fabric <- mkAXI4_Fabric(fn_addr_to_slave_num);
166 // Connect traffic generators to fabric
167 mkConnection (core.dmem_master,fabric.v_from_masters
168 [fromInteger(valueOf(Dmem_master_num))]);
169 mkConnection (core.imem_master, fabric.v_from_masters
170 [fromInteger(valueOf(Imem_master_num))]);
172 mkConnection (core.debug_master, fabric.v_from_masters
173 [fromInteger(valueOf(Debug_master_num))]);
176 mkConnection (dma.mmu, fabric.v_from_masters
177 [fromInteger(valueOf(DMA_master_num))]);
181 // Connect fabric to memory slaves
183 mkConnection (fabric.v_to_slaves
184 [fromInteger(valueOf(Debug_slave_num))],
188 mkConnection (fabric.v_to_slaves
189 [fromInteger(valueOf(Sdram_slave_num))],
190 sdram.axi4_slave_sdram); //
191 mkConnection (fabric.v_to_slaves
192 [fromInteger(valueOf(Sdram_cfg_slave_num))],
193 sdram.axi4_slave_cntrl_reg); //
196 mkConnection(fabric.v_to_slaves
197 [fromInteger(valueOf(Sdram_slave_num))],
198 main_memory.axi_slave);
201 mkConnection (fabric.v_to_slaves
202 [fromInteger(valueOf(BootRom_slave_num))],
206 mkConnection (fabric.v_to_slaves
207 [fromInteger(valueOf(Dma_slave_num))],
208 dma.cfg); //DMA slave
211 mkConnection (fabric.v_to_slaves
212 [fromInteger(valueOf(TCM_slave_num))],
215 mkConnection(fabric.v_to_slaves
216 [fromInteger(valueOf(SlowPeripheral_slave_num))],
217 slow_peripherals.axi_slave);
219 mkConnection (fabric.v_to_slaves
220 [fromInteger(valueOf(VME_slave_num))],
224 mkConnection (fabric.v_to_slaves
225 [fromInteger(valueOf(FlexBus_slave_num))],
229 // fabric connections
233 // rule to connect all interrupt lines to the DMA
234 // All the interrupt lines to DMA are active
235 // HIGH. For peripherals that are not connected,
236 // or those which do not
237 // generate an interrupt (like TCM), drive a constant 1
238 // on the corresponding interrupt line.
243 /*==== Synchornization between the JTAG and the Debug Module ===== */
245 SyncFIFOIfc#(Bit#(40)) sync_request_to_dm <-
246 mkSyncFIFOToCC(1,tck,trst);
247 SyncFIFOIfc#(Bit#(34)) sync_response_from_dm <-
248 mkSyncFIFOFromCC(1,tck);
249 rule connect_tap_request_to_syncfifo;
250 let x<-tap.request_to_dm;
251 sync_request_to_dm.enq(x);
253 rule read_synced_request_to_dm;
254 sync_request_to_dm.deq;
255 core.request_from_dtm(sync_request_to_dm.first);
258 rule connect_debug_response_to_syncfifo;
259 let x<-core.response_to_dtm;
260 sync_response_from_dm.enq(x);
262 rule read_synced_response_from_dm;
263 sync_response_from_dm.deq;
264 tap.response_from_dm(sync_response_from_dm.first);
267 /*============================================================ */
270 //rule drive_flexbus_inputs;
271 //flexbus.flexbus_side.m_TAn(1'b1);
272 //flexbus.flexbus_side.m_din(32'haaaaaaaa);
277 SyncBitIfc#(Bit#(1)) clint_mtip_int <-
278 mkSyncBitToCC(slow_clock,slow_reset);
279 SyncBitIfc#(Bit#(1)) clint_msip_int <-
280 mkSyncBitToCC(slow_clock,slow_reset);
281 Reg#(Bit#(`Reg_width)) clint_mtime_value <-
282 mkSyncRegToCC(0,slow_clock,slow_reset);
283 rule synchronize_clint_data;
284 clint_mtip_int.send(slow_peripherals.mtip_int);
285 clint_msip_int.send(slow_peripherals.msip_int);
286 clint_mtime_value<=slow_peripherals.mtime;
288 rule connect_msip_mtip_from_clint;
289 core.clint_msip(clint_msip_int.read);
290 core.clint_mtip(clint_mtip_int.read);
291 core.clint_mtime(clint_mtime_value);
295 Reg#(Tuple2#(Bool,Bool)) plic_interrupt_note <-
296 mkSyncRegToCC(tuple2(False,False),
297 slow_clock,slow_reset);
298 rule synchronize_interrupts;
299 let note <- slow_peripherals.intrpt_note;
300 plic_interrupt_note<=note;
302 rule rl_send_external_interrupt_to_csr;
303 core.set_external_interrupt(plic_interrupt_note);
308 interface proc_ifc = vme.proc_ifc;
309 interface proc_dbus = vme.proc_dbus;
312 interface flexbus_out = flexbus.flexbus_side;
314 method Action boot_sequence(Bit#(1) bootseq) =
315 core.boot_sequence(bootseq);
317 interface sdram_out=sdram.ifc_sdram_out;
320 interface master=fabric.v_to_slaves
321 [fromInteger(valueOf(Sdram_slave_num))];
323 interface slow_ios=slow_peripherals.slow_ios;