2 Copyright (c) 2013, IIT Madras
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24 TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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28 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 -------------------------------------------------------------------
32 /*====== Package imports === */
35 import SpecialFIFOs::*;
37 import ClientServer::*;
39 import Connectable::*;
42 /*=== Project imports === */
45 import AXI4_Fabric::*;
46 import defined_types::*;
47 import MemoryMap :: *;
48 import slow_peripherals::*;
49 import fast_memory_map::*;
50 import slow_memory_map::*;
52 `include "defines.bsv"
54 `include "instance_defines.bsv"
55 `include "core_parameters.bsv"
68 import Memory_AXI4 ::*;
74 import DebugModule::*;
86 import FlexBus_Types::*;
90 /*========================= */
92 interface SP_dedicated_ios slow_ios;
93 (*always_ready,always_enabled*)
94 method Action boot_sequence(Bit#(1) bootseq);
97 (*always_ready*) interface Ifc_sdram_out sdram_out;
100 (*prefix="M_AXI"*) interface
101 AXI4_Master_IFC#(`PADDR, `DATA, `USERSPACE) master;
104 (*always_ready,always_enabled*)
105 interface Ifc_flash ifc_flash;
107 /*=============================================== */
109 interface Vme_out proc_ifc;
110 interface Data_bus_inf proc_dbus;
115 //============ mkSoc module =================
118 module mkSoc #(Bit#(`VADDR) reset_vector,
119 Clock slow_clock, Reset slow_reset, Clock uart_clock,
120 Reset uart_reset, Clock clk0, Clock tck, Reset trst
121 `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif )(Ifc_Soc);
122 Clock core_clock <-exposeCurrentClock; // slow peripheral clock
123 Reset core_reset <-exposeCurrentReset; // slow peripheral reset
126 Ifc_DebugModule core<-mkDebugModule(reset_vector);
128 Ifc_core_AXI4 core <-mkcore_AXI4(reset_vector);
131 BootRom_IFC bootrom <-mkBootRom;
134 Ifc_sdr_slave sdram<- mksdr_axi4_slave(clk0);
137 Memory_IFC#(`SDRAMMemBase,`Addr_space)main_memory <-
138 mkMemory("code.mem.MSB","code.mem.LSB","MainMEM");
141 Ifc_TCM tcm <- mkTCM;
144 DmaC#(7,`NUM_DMACHANNELS) dma <- mkDMA();
147 Ifc_vme_top vme <-mkvme_top();
149 Ifc_slow_peripherals slow_peripherals <-mkslow_peripherals(
150 core_clock, core_reset, uart_clock,
151 uart_reset, clocked_by slow_clock ,
153 `ifdef PWM_AXI4Lite , ext_pwm_clock `endif );
156 AXI4_Fabric_IFC #(Num_Masters, Num_Fast_Slaves,
157 `PADDR, `DATA,`USERSPACE)
158 fabric <- mkAXI4_Fabric(fn_addr_to_slave_num);
160 // Connect traffic generators to fabric
161 mkConnection (core.dmem_master,fabric.v_from_masters
162 [fromInteger(valueOf(Dmem_master_num))]);
163 mkConnection (core.imem_master, fabric.v_from_masters
164 [fromInteger(valueOf(Imem_master_num))]);
166 mkConnection (core.debug_master, fabric.v_from_masters
167 [fromInteger(valueOf(Debug_master_num))]);
170 mkConnection (dma.mmu, fabric.v_from_masters
171 [fromInteger(valueOf(DMA_master_num))]);
175 // Connect fabric to memory slaves
177 mkConnection (fabric.v_to_slaves
178 [fromInteger(valueOf(Debug_slave_num))],
182 mkConnection (fabric.v_to_slaves
183 [fromInteger(valueOf(Sdram_slave_num))],
184 sdram.axi4_slave_sdram); //
185 mkConnection (fabric.v_to_slaves
186 [fromInteger(valueOf(Sdram_cfg_slave_num))],
187 sdram.axi4_slave_cntrl_reg); //
190 mkConnection(fabric.v_to_slaves
191 [fromInteger(valueOf(Sdram_slave_num))],
192 main_memory.axi_slave);
195 mkConnection (fabric.v_to_slaves
196 [fromInteger(valueOf(BootRom_slave_num))],
200 mkConnection (fabric.v_to_slaves
201 [fromInteger(valueOf(Dma_slave_num))],
202 dma.cfg); //DMA slave
205 mkConnection (fabric.v_to_slaves
206 [fromInteger(valueOf(TCM_slave_num))],
209 mkConnection(fabric.v_to_slaves
210 [fromInteger(valueOf(SlowPeripheral_slave_num))],
211 slow_peripherals.axi_slave);
213 mkConnection (fabric.v_to_slaves
214 [fromInteger(valueOf(VME_slave_num))],
221 // fabric connections
225 // rule to connect all interrupt lines to the DMA
226 // All the interrupt lines to DMA are active
227 // HIGH. For peripherals that are not connected,
228 // or those which do not
229 // generate an interrupt (like TCM), drive a constant 1
230 // on the corresponding interrupt line.
235 /*==== Synchornization between the JTAG and the Debug Module ===== */
237 SyncFIFOIfc#(Bit#(40)) sync_request_to_dm <-
238 mkSyncFIFOToCC(1,tck,trst);
239 SyncFIFOIfc#(Bit#(34)) sync_response_from_dm <-
240 mkSyncFIFOFromCC(1,tck);
241 rule connect_tap_request_to_syncfifo;
242 let x<-tap.request_to_dm;
243 sync_request_to_dm.enq(x);
245 rule read_synced_request_to_dm;
246 sync_request_to_dm.deq;
247 core.request_from_dtm(sync_request_to_dm.first);
250 rule connect_debug_response_to_syncfifo;
251 let x<-core.response_to_dtm;
252 sync_response_from_dm.enq(x);
254 rule read_synced_response_from_dm;
255 sync_response_from_dm.deq;
256 tap.response_from_dm(sync_response_from_dm.first);
259 /*============================================================ */
262 //rule drive_flexbus_inputs;
263 //flexbus.flexbus_side.m_TAn(1'b1);
264 //flexbus.flexbus_side.m_din(32'haaaaaaaa);
269 SyncBitIfc#(Bit#(1)) clint_mtip_int <-
270 mkSyncBitToCC(slow_clock,slow_reset);
271 SyncBitIfc#(Bit#(1)) clint_msip_int <-
272 mkSyncBitToCC(slow_clock,slow_reset);
273 Reg#(Bit#(`DATA)) clint_mtime_value <-
274 mkSyncRegToCC(0,slow_clock,slow_reset);
275 rule synchronize_clint_data;
276 clint_mtip_int.send(slow_peripherals.mtip_int);
277 clint_msip_int.send(slow_peripherals.msip_int);
278 clint_mtime_value<=slow_peripherals.mtime;
280 rule connect_msip_mtip_from_clint;
281 core.clint_msip(clint_msip_int.read);
282 core.clint_mtip(clint_mtip_int.read);
283 core.clint_mtime(clint_mtime_value);
287 Reg#(Tuple2#(Bool,Bool)) plic_interrupt_note <-
288 mkSyncRegToCC(tuple2(False,False),
289 slow_clock,slow_reset);
290 rule synchronize_interrupts;
291 let note <- slow_peripherals.intrpt_note;
292 plic_interrupt_note<=note;
294 rule rl_send_external_interrupt_to_csr;
295 core.set_external_interrupt(plic_interrupt_note);
300 interface proc_ifc = vme.proc_ifc;
301 interface proc_dbus = vme.proc_dbus;
303 method Action boot_sequence(Bit#(1) bootseq) =
304 core.boot_sequence(bootseq);
306 interface sdram_out=sdram.ifc_sdram_out;
309 interface master=fabric.v_to_slaves
310 [fromInteger(valueOf(Sdram_slave_num))];
312 interface slow_ios=slow_peripherals.slow_ios;