2 Copyright (c) 2013, IIT Madras
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6 modification, are permitted provided that the following conditions
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14 * Neither the name of IIT Madras nor the names of its contributors
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16 without specific prior written permission.
18 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21 A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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23 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
24 TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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27 NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 -------------------------------------------------------------------
32 /*====== Package imports === */
35 import SpecialFIFOs::*;
37 import ClientServer::*;
39 import Connectable::*;
41 /*========================== */
43 /*=== Project imports === */
46 import AXI4_Fabric::*;
47 import defined_types::*;
48 import MemoryMap :: *;
49 import slow_peripherals::*;
51 `include "defines.bsv"
53 `include "instance_defines.bsv"
54 `include "core_parameters.bsv"
56 /*====== AXI4 slave declarations =======*/
58 /*====== AXI4 Master declarations =======*/
72 import Memory_AXI4 ::*;
78 import DebugModule::*;
90 import FlexBus_Types::*;
94 /*========================= */
96 interface SP_ios slow_ios;
97 (*always_ready,always_enabled*)
98 method Action boot_sequence(Bit#(1) bootseq);
101 (*always_ready*) interface Ifc_sdram_out sdram_out;
104 (*prefix="M_AXI"*) interface
105 AXI4_Master_IFC#(`ADDR, `DATA, `USERSPACE) master;
108 (*always_ready,always_enabled*)
109 interface Ifc_flash ifc_flash;
111 /*=============================================== */
113 interface Vme_out proc_ifc;
114 interface Data_bus_inf proc_dbus;
119 function FastTuple2 #(Bool, Bit#(TLog#(Num_Slaves)))
120 fn_addr_to_slave_num (Bit#(`PADDR) addr);
122 if(addr>=`SDRAMMemBase && addr<=`SDRAMMemEnd)
123 return tuple2(True,fromInteger(valueOf(Sdram_slave_num)));
124 else if(addr>=`DebugBase && addr<=`DebugEnd)
125 return tuple2(True,fromInteger(valueOf(Debug_slave_num)));
127 else if(addr>=`SDRAMCfgBase && addr<=`SDRAMCfgEnd )
128 return tuple2(True,fromInteger(valueOf(Sdram_cfg_slave_num)));
131 else if(addr>=`BootRomBase && addr<=`BootRomEnd)
132 return tuple2(True,fromInteger(valueOf(BootRom_slave_num)));
135 else if(addr>=`DMABase && addr<=`DMAEnd)
136 return tuple2(True,fromInteger(valueOf(Dma_slave_num)));
139 else if(addr>=`VMEBase && addr<=`VMEEnd)
140 return tuple2(True,fromInteger(valueOf(VME_slave_num)));
143 else if(addr>=`TCMBase && addr<=`TCMEnd)
144 return tuple2(True,fromInteger(valueOf(TCM_slave_num)));
148 return tuple2(False,?);
153 module mkSoc #(Bit#(`VADDR) reset_vector,
154 Clock slow_clock, Reset slow_reset, Clock uart_clock,
155 Reset uart_reset, Clock clk0, Clock tck, Reset trst
156 `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif )(Ifc_Soc);
157 Clock core_clock <-exposeCurrentClock; // slow peripheral clock
158 Reset core_reset <-exposeCurrentReset; // slow peripheral reset
161 Ifc_DebugModule core<-mkDebugModule(reset_vector);
163 Ifc_core_AXI4 core <-mkcore_AXI4(reset_vector);
166 BootRom_IFC bootrom <-mkBootRom;
169 Ifc_sdr_slave sdram<- mksdr_axi4_slave(clk0);
172 Memory_IFC#(`SDRAMMemBase,`Addr_space)main_memory <-
173 mkMemory("code.mem.MSB","code.mem.LSB","MainMEM");
176 Ifc_TCM tcm <- mkTCM;
179 DmaC#(7,`NUM_DMACHANNELS) dma <- mkDMA();
182 Ifc_vme_top vme <-mkvme_top();
184 Ifc_slow_peripherals slow_peripherals <-mkslow_peripherals(
185 core_clock, core_reset, uart_clock,
186 uart_reset, clocked_by slow_clock ,
188 `ifdef PWM_AXI4Lite , ext_pwm_clock `endif );
191 AXI4_Fabric_IFC #(Num_Masters, Num_Slaves,
192 `ADDR, `DATA,`USERSPACE)
193 fabric <- mkAXI4_Fabric(fn_addr_to_slave_num);
195 // Connect traffic generators to fabric
196 mkConnection (core.dmem_master,fabric.v_from_masters
197 [fromInteger(valueOf(Dmem_master_num))]);
198 mkConnection (core.imem_master, fabric.v_from_masters
199 [fromInteger(valueOf(Imem_master_num))]);
201 mkConnection (core.debug_master, fabric.v_from_masters
202 [fromInteger(valueOf(Debug_master_num))]);
205 mkConnection (dma.mmu, fabric.v_from_masters
206 [fromInteger(valueOf(DMA_master_num))]);
210 // Connect fabric to memory slaves
212 mkConnection (fabric.v_to_slaves
213 [fromInteger(valueOf(Debug_slave_num))],
217 mkConnection (fabric.v_to_slaves
218 [fromInteger(valueOf(Sdram_slave_num))],
219 sdram.axi4_slave_sdram); //
220 mkConnection (fabric.v_to_slaves
221 [fromInteger(valueOf(Sdram_cfg_slave_num))],
222 sdram.axi4_slave_cntrl_reg); //
225 mkConnection(fabric.v_to_slaves
226 [fromInteger(valueOf(Sdram_slave_num))],
227 main_memory.axi_slave);
230 mkConnection (fabric.v_to_slaves
231 [fromInteger(valueOf(BootRom_slave_num))],
235 mkConnection (fabric.v_to_slaves
236 [fromInteger(valueOf(Dma_slave_num))],
237 dma.cfg); //DMA slave
240 mkConnection (fabric.v_to_slaves
241 [fromInteger(valueOf(TCM_slave_num))],
244 mkConnection(fabric.v_to_slaves
245 [fromInteger(valueOf(SlowPeripheral_slave_num))],
246 slow_peripherals.axi_slave);
248 mkConnection (fabric.v_to_slaves
249 [fromInteger(valueOf(VME_slave_num))],
256 // fabric connections
260 // rule to connect all interrupt lines to the DMA
261 // All the interrupt lines to DMA are active
262 // HIGH. For peripherals that are not connected,
263 // or those which do not
264 // generate an interrupt (like TCM), drive a constant 1
265 // on the corresponding interrupt line.
270 /*==== Synchornization between the JTAG and the Debug Module ===== */
272 SyncFIFOIfc#(Bit#(40)) sync_request_to_dm <-
273 mkSyncFIFOToCC(1,tck,trst);
274 SyncFIFOIfc#(Bit#(34)) sync_response_from_dm <-
275 mkSyncFIFOFromCC(1,tck);
276 rule connect_tap_request_to_syncfifo;
277 let x<-tap.request_to_dm;
278 sync_request_to_dm.enq(x);
280 rule read_synced_request_to_dm;
281 sync_request_to_dm.deq;
282 core.request_from_dtm(sync_request_to_dm.first);
285 rule connect_debug_response_to_syncfifo;
286 let x<-core.response_to_dtm;
287 sync_response_from_dm.enq(x);
289 rule read_synced_response_from_dm;
290 sync_response_from_dm.deq;
291 tap.response_from_dm(sync_response_from_dm.first);
294 /*============================================================ */
297 //rule drive_flexbus_inputs;
298 //flexbus.flexbus_side.m_TAn(1'b1);
299 //flexbus.flexbus_side.m_din(32'haaaaaaaa);
304 SyncBitIfc#(Bit#(1)) clint_mtip_int <-
305 mkSyncBitToCC(slow_clock,slow_reset);
306 SyncBitIfc#(Bit#(1)) clint_msip_int <-
307 mkSyncBitToCC(slow_clock,slow_reset);
308 Reg#(Bit#(`DATA)) clint_mtime_value <-
309 mkSyncRegToCC(0,slow_clock,slow_reset);
310 rule synchronize_clint_data;
311 clint_mtip_int.send(slow_peripherals.mtip_int);
312 clint_msip_int.send(slow_peripherals.msip_int);
313 clint_mtime_value<=slow_peripherals.mtime;
315 rule connect_msip_mtip_from_clint;
316 core.clint_msip(clint_msip_int.read);
317 core.clint_mtip(clint_mtip_int.read);
318 core.clint_mtime(clint_mtime_value);
322 Reg#(Tuple2#(Bool,Bool)) plic_interrupt_note <-
323 mkSyncRegToCC(tuple2(False,False),
324 slow_clock,slow_reset);
325 rule synchronize_interrupts;
326 let note <- slow_peripherals.intrpt_note;
327 plic_interrupt_note<=note;
329 rule rl_send_external_interrupt_to_csr;
330 core.set_external_interrupt(plic_interrupt_note);
335 interface proc_ifc = vme.proc_ifc;
336 interface proc_dbus = vme.proc_dbus;
338 method Action boot_sequence(Bit#(1) bootseq) =
339 core.boot_sequence(bootseq);
341 interface sdram_out=sdram.ifc_sdram_out;
344 interface master=fabric.v_to_slaves
345 [fromInteger(valueOf(Sdram_slave_num))];
347 interface slow_ios=slow_peripherals.slow_ios;