2 Copyright (c) 2013, IIT Madras
5 Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
7 * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
8 * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
9 * Neither the name of IIT Madras nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
11 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
12 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
15 /*====== Package imports === */
18 import SpecialFIFOs::*;
20 import ClientServer::*;
22 import Connectable::*;
24 /*========================== */
25 /*=== Project imports === */
28 import AXI4_Fabric::*;
29 import defined_types::*;
30 import MemoryMap :: *;
31 import slow_peripherals::*;
32 `include "defines.bsv"
33 `include "instance_defines.bsv"
45 import Memory_AXI4 ::*;
52 import DebugModule::*;
64 import FlexBus_Types::*;
67 /*========================= */
69 interface SP_ios slow_ios;
70 (*always_ready,always_enabled*)
71 method Action boot_sequence(Bit#(1) bootseq);
74 (*always_ready*) interface Ifc_sdram_out sdram_out;
77 (*prefix="M_AXI"*) interface AXI4_Master_IFC#(`PADDR, `Reg_width, `USERSPACE) master;
80 (*always_ready,always_enabled*)
81 method Action tms_i(Bit#(1) tms);
82 (*always_ready,always_enabled*)
83 method Action tdi_i(Bit#(1) tdi);
84 (*always_ready,always_enabled*)
85 method Action bs_chain_i(Bit#(1) bs_chain);
86 (*always_ready,always_enabled*)
87 method Bit#(1) shiftBscan2Edge;
88 (*always_ready,always_enabled*)
89 method Bit#(1) selectJtagInput;
90 (*always_ready,always_enabled*)
91 method Bit#(1) selectJtagOutput;
92 (*always_ready,always_enabled*)
93 method Bit#(1) updateBscan;
94 (*always_ready,always_enabled*)
95 method Bit#(1) bscan_in;
96 (*always_ready,always_enabled*)
97 method Bit#(1) scan_shift_en;
98 (*always_ready,always_enabled*)
100 (*always_ready,always_enabled*)
101 method Bit#(1) tdo_oe;
104 (*always_ready,always_enabled*)
105 interface Ifc_flash ifc_flash;
107 /*=============================================== */
109 interface Vme_out proc_ifc;
110 interface Data_bus_inf proc_dbus;
113 interface FlexBus_Master_IFC flexbus_out;
118 module mkSoc #(Bit#(`VADDR) reset_vector, Clock slow_clock, Reset slow_reset, Clock uart_clock,
119 Reset uart_reset, Clock clk0, Clock tck, Reset trst
120 `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif )(Ifc_Soc);
121 Clock core_clock <-exposeCurrentClock; // slow peripheral clock
122 Reset core_reset <-exposeCurrentReset; // slow peripheral reset
124 Ifc_jtagdtm tap <-mkjtagdtm(clocked_by tck, reset_by trst);
125 rule drive_tmp_scan_outs;
126 tap.scan_out_1_i(1'b0);
127 tap.scan_out_2_i(1'b0);
128 tap.scan_out_3_i(1'b0);
129 tap.scan_out_4_i(1'b0);
130 tap.scan_out_5_i(1'b0);
132 Ifc_DebugModule core<-mkDebugModule(reset_vector);
134 Ifc_core_AXI4 core <-mkcore_AXI4(reset_vector);
137 BootRom_IFC bootrom <-mkBootRom;
140 Ifc_sdr_slave sdram <- mksdr_axi4_slave(clk0);
143 Memory_IFC#(`SDRAMMemBase,`Addr_space) main_memory <- mkMemory("code.mem.MSB","code.mem.LSB","MainMEM");
146 Ifc_TCM tcm <- mkTCM;
149 DmaC#(7,12) dma <- mkDMA();
152 Ifc_vme_top vme <-mkvme_top();
155 AXI4_Slave_to_FlexBus_Master_Xactor_IFC #(32, 64,0)
156 flexbus <- mkAXI4_Slave_to_FlexBus_Master_Xactor;
158 Ifc_slow_peripherals slow_peripherals <-mkslow_peripherals(core_clock, core_reset, uart_clock,
159 uart_reset, clocked_by slow_clock , reset_by slow_reset
160 `ifdef PWM_AXI4Lite , ext_pwm_clock `endif );
163 AXI4_Fabric_IFC #(Num_Masters, Num_Slaves, `PADDR, `Reg_width,`USERSPACE)
164 fabric <- mkAXI4_Fabric(fn_addr_to_slave_num);
166 // Connect traffic generators to fabric
167 mkConnection (core.dmem_master, fabric.v_from_masters [fromInteger(valueOf(Dmem_master_num))]);
168 mkConnection (core.imem_master, fabric.v_from_masters [fromInteger(valueOf(Imem_master_num))]);
170 mkConnection (core.debug_master, fabric.v_from_masters [fromInteger(valueOf(Debug_master_num))]);
173 mkConnection (dma.mmu, fabric.v_from_masters[fromInteger(valueOf(DMA_master_num))]);
177 // Connect fabric to memory slaves
179 mkConnection (fabric.v_to_slaves [fromInteger(valueOf(Debug_slave_num))],core.debug_slave);
182 mkConnection (fabric.v_to_slaves [fromInteger(valueOf(Sdram_slave_num))], sdram.axi4_slave_sdram); //
183 mkConnection (fabric.v_to_slaves [fromInteger(valueOf(Sdram_cfg_slave_num))], sdram.axi4_slave_cntrl_reg); //
186 mkConnection(fabric.v_to_slaves[fromInteger(valueOf(Sdram_slave_num))],main_memory.axi_slave);
189 mkConnection (fabric.v_to_slaves [fromInteger(valueOf(BootRom_slave_num))],bootrom.axi_slave);
192 mkConnection (fabric.v_to_slaves [fromInteger(valueOf(Dma_slave_num))], dma.cfg); //DMA slave
195 mkConnection (fabric.v_to_slaves [fromInteger(valueOf(TCM_slave_num))],tcm.axi_slave);
197 mkConnection(fabric.v_to_slaves [fromInteger(valueOf(SlowPeripheral_slave_num))],slow_peripherals.axi_slave);
199 mkConnection (fabric.v_to_slaves[fromInteger(valueOf(VME_slave_num))],vme.slave_axi_vme);
202 mkConnection (fabric.v_to_slaves[fromInteger(valueOf(FlexBus_slave_num))],flexbus.axi_side);
205 //rule to connect all interrupt lines to the DMA
206 //All the interrupt lines to DMA are active HIGH. For peripherals that are not connected, or those which do not
207 //generate an interrupt (like TCM), drive a constant 1 on the corresponding interrupt line.
208 `ifdef I2C1 SyncBitIfc#(Bit#(1)) i2c1_interrupt <-mkSyncBitToCC(slow_clock,slow_reset); `endif
209 `ifdef I2C0 SyncBitIfc#(Bit#(1)) i2c0_interrupt <-mkSyncBitToCC(slow_clock,slow_reset); `endif
210 `ifdef QSPI1 SyncBitIfc#(Bit#(1)) qspi1_interrupt <-mkSyncBitToCC(slow_clock,slow_reset); `endif
211 `ifdef QSPI0 SyncBitIfc#(Bit#(1)) qspi0_interrupt <-mkSyncBitToCC(slow_clock,slow_reset); `endif
212 `ifdef UART0 SyncBitIfc#(Bit#(1)) uart0_interrupt <-mkSyncBitToCC(uart_clock,uart_reset); `endif
213 rule synchronize_i2c_interrupts;
214 `ifdef I2C1 i2c1_interrupt.send(slow_peripherals.i2c1_isint); `endif
215 `ifdef I2C0 i2c0_interrupt.send(slow_peripherals.i2c0_isint); `endif
217 rule synchronize_qspi_interrupts;
218 `ifdef QSPI0 qspi0_interrupt.send(slow_peripherals.qspi0_isint); `endif
219 `ifdef QSPI1 qspi1_interrupt.send(slow_peripherals.qspi1_isint); `endif
221 rule synchronize_uart0_interrupt;
222 `ifdef UART0 uart0_interrupt.send(slow_peripherals.uart0_intr); `endif
224 rule rl_connect_interrupt_to_DMA;
225 Bit#(12) lv_interrupt_to_DMA= {'d-1,
226 `ifdef I2C1 i2c1_interrupt.read `else 1'b1 `endif ,
227 `ifdef I2C0 i2c0_interrupt.read `else 1'b1 `endif ,
228 `ifdef QSPI1 qspi1_interrupt.read `else 1'b1 `endif ,
230 `ifdef QSPI0 qspi0_interrupt.read `else 1'b1 `endif ,
232 `ifdef UART0 uart0_interrupt.read `else 1'b1 `endif };
233 dma.interrupt_from_peripherals(lv_interrupt_to_DMA);
238 /*======= Synchornization between the JTAG and the Debug Module ========= */
240 SyncFIFOIfc#(Bit#(40)) sync_request_to_dm <-mkSyncFIFOToCC(1,tck,trst);
241 SyncFIFOIfc#(Bit#(34)) sync_response_from_dm <-mkSyncFIFOFromCC(1,tck);
242 rule connect_tap_request_to_syncfifo;
243 let x<-tap.request_to_dm;
244 sync_request_to_dm.enq(x);
246 rule read_synced_request_to_dm;
247 sync_request_to_dm.deq;
248 core.request_from_dtm(sync_request_to_dm.first);
251 rule connect_debug_response_to_syncfifo;
252 let x<-core.response_to_dtm;
253 sync_response_from_dm.enq(x);
255 rule read_synced_response_from_dm;
256 sync_response_from_dm.deq;
257 tap.response_from_dm(sync_response_from_dm.first);
260 /*======================================================================= */
263 //rule drive_flexbus_inputs;
264 //flexbus.flexbus_side.m_TAn(1'b1);
265 //flexbus.flexbus_side.m_din(32'haaaaaaaa);
270 SyncBitIfc#(Bit#(1)) clint_mtip_int <-mkSyncBitToCC(slow_clock,slow_reset);
271 SyncBitIfc#(Bit#(1)) clint_msip_int <-mkSyncBitToCC(slow_clock,slow_reset);
272 Reg#(Bit#(`Reg_width)) clint_mtime_value <-mkSyncRegToCC(0,slow_clock,slow_reset);
273 rule synchronize_clint_data;
274 clint_mtip_int.send(slow_peripherals.mtip_int);
275 clint_msip_int.send(slow_peripherals.msip_int);
276 clint_mtime_value<=slow_peripherals.mtime;
278 rule connect_msip_mtip_from_clint;
279 core.clint_msip(clint_msip_int.read);
280 core.clint_mtip(clint_mtip_int.read);
281 core.clint_mtime(clint_mtime_value);
285 Reg#(Tuple2#(Bool,Bool)) plic_interrupt_note <-mkSyncRegToCC(tuple2(False,False),slow_clock,slow_reset);
286 rule synchronize_interrupts;
287 let note <- slow_peripherals.intrpt_note;
288 plic_interrupt_note<=note;
290 rule rl_send_external_interrupt_to_csr;
291 core.set_external_interrupt(plic_interrupt_note);
296 interface proc_ifc = vme.proc_ifc;
297 interface proc_dbus = vme.proc_dbus;
300 interface flexbus_out = flexbus.flexbus_side;
302 method Action boot_sequence(Bit#(1) bootseq) = core.boot_sequence(bootseq);
304 interface sdram_out=sdram.ifc_sdram_out;
307 interface master=fabric.v_to_slaves[fromInteger(valueOf(Sdram_slave_num))];
310 method Action tms_i(Bit#(1) tms);
313 method Action tdi_i(Bit#(1) tdi);
316 method Action bs_chain_i(Bit#(1) bs_chain);
317 tap.bs_chain_i(bs_chain);
319 method Bit#(1) shiftBscan2Edge=tap.shiftBscan2Edge;
320 method Bit#(1) selectJtagInput=tap.selectJtagInput;
321 method Bit#(1) selectJtagOutput=tap.selectJtagOutput;
322 method Bit#(1) updateBscan=tap.updateBscan;
323 method Bit#(1) bscan_in=tap.bscan_in;
324 method Bit#(1) scan_shift_en=tap.scan_shift_en;
325 method Bit#(1) tdo=tap.tdo;
326 method Bit#(1) tdo_oe=tap.tdo_oe;
328 interface slow_ios=slow_peripherals.slow_ios;