4 from UserDict
import UserDict
6 from collections
import UserDict
8 from bsv
.wire_def
import generic_io
# special case
9 from bsv
.wire_def
import muxwire
# special case
13 """ pin interface declaration.
14 * name is the name of the pin
15 * ready, enabled and io all create a (* .... *) prefix
16 * action changes it to an "in" if true
19 def __init__(self
, name
,
28 self
.enabled
= enabled
31 self
.bitspec
= bitspec
if bitspec
else 'Bit#(1)'
32 self
.outenmode
= outenmode
34 def ifacefmt(self
, fmtfn
):
38 status
.append('always_ready')
40 status
.append('always_enabled')
42 status
.append('result="io"')
45 res
+= ','.join(status
)
50 name
= fmtfn(self
.name
)
54 res
+= ' (%s in)' % self
.bitspec
56 res
+= " %s " % self
.bitspec
61 def ifacedef(self
, fmtoutfn
, fmtinfn
, fmtdecfn
):
64 fmtname
= fmtinfn(self
.name
)
66 res
+= fmtdecfn(self
.name
)
67 res
+= '(%s in);\n' % self
.bitspec
68 res
+= ' %s<=in;\n' % fmtname
71 fmtname
= fmtoutfn(self
.name
)
72 res
+= "%s=%s;" % (self
.name
, fmtname
)
75 def wirefmt(self
, fmtoutfn
, fmtinfn
, fmtdecfn
):
76 res
= ' Wire#(%s) ' % self
.bitspec
78 res
+= '%s' % fmtinfn(self
.name
)
80 res
+= '%s' % fmtoutfn(self
.name
)
81 res
+= "<-mkDWire(0);"
85 class Interface(object):
86 """ create an interface from a list of pinspecs.
87 each pinspec is a dictionary, see Pin class arguments
88 single indicates that there is only one of these, and
89 so the name must *not* be extended numerically (see pname)
92 def __init__(self
, ifacename
, pinspecs
, ganged
=None, single
=False):
93 self
.ifacename
= ifacename
94 self
.ganged
= ganged
or {}
96 self
.pinspecs
= pinspecs
101 if p
.get('outen') is True: # special case, generate 3 pins
103 for psuffix
in ['out', 'outen', 'in']:
104 _p
['name'] = "%s_%s" % (self
.pname(p
['name']), psuffix
)
105 _p
['action'] = psuffix
!= 'in'
106 self
.pins
.append(Pin(**_p
))
108 _p
['name'] = self
.pname(p
['name'])
109 self
.pins
.append(Pin(**_p
))
111 def getifacetype(self
, name
):
112 for p
in self
.pinspecs
:
113 fname
= "%s_%s" % (self
.ifacename
, p
['name'])
114 #print "search", self.ifacename, name, fname
123 def pname(self
, name
):
124 """ generates the interface spec e.g. flexbus_ale
125 if there is only one flexbus interface, or
126 sd{0}_cmd if there are several. string format
127 function turns this into sd0_cmd, sd1_cmd as
128 appropriate. single mode stops the numerical extension.
131 return '%s_%s' % (self
.ifacename
, name
)
132 return '%s{0}_%s' % (self
.ifacename
, name
)
134 def busfmt(self
, *args
):
135 """ this function creates a bus "ganging" system based
136 on input from the {interfacename}.txt file.
137 only inout pins that are under the control of the
138 interface may be "ganged" together.
144 for (k
, pnames
) in self
.ganged
.items():
145 name
= self
.pname('%senable' % k
).format(*args
)
146 decl
= 'Bit#(1) %s = 0;' % name
149 for p
in self
.pinspecs
:
150 if p
['name'] not in pnames
:
152 pname
= self
.pname(p
['name']).format(*args
)
153 if p
.get('outen') is True:
154 outname
= self
.ifacefmtoutfn(pname
)
155 ganged
.append("%s_outen" % outname
) # match wirefmt
157 gangedfmt
= '{%s} = duplicate(%s);'
158 res
.append(gangedfmt
% (',\n '.join(ganged
), name
))
159 return '\n'.join(res
) + '\n\n'
161 def wirefmt(self
, *args
):
162 res
= '\n'.join(map(self
.wirefmtpin
, self
.pins
)).format(*args
)
166 def ifacefmt(self
, *args
):
167 res
= '\n'.join(map(self
.ifacefmtdecpin
, self
.pins
)).format(*args
)
170 def ifacefmtdecfn(self
, name
):
173 def ifacefmtdecfn2(self
, name
):
176 def ifacefmtdecfn3(self
, name
):
178 return "%s_outen" % name
180 def ifacefmtoutfn(self
, name
):
183 def ifacefmtinfn(self
, name
):
186 def wirefmtpin(self
, pin
):
187 return pin
.wirefmt(self
.ifacefmtoutfn
, self
.ifacefmtinfn
,
190 def ifacefmtdecpin(self
, pin
):
191 return pin
.ifacefmt(self
.ifacefmtdecfn
)
193 def ifacefmtpin(self
, pin
):
194 decfn
= self
.ifacefmtdecfn2
195 outfn
= self
.ifacefmtoutfn
196 #print pin, pin.outenmode
198 decfn
= self
.ifacefmtdecfn3
199 outfn
= self
.ifacefmtoutenfn
200 return pin
.ifacedef(outfn
, self
.ifacefmtinfn
,
203 def ifacedef(self
, *args
):
204 res
= '\n'.join(map(self
.ifacefmtpin
, self
.pins
))
205 res
= res
.format(*args
)
206 return '\n' + res
+ '\n'
209 class MuxInterface(Interface
):
211 def wirefmt(self
, *args
):
212 return muxwire
.format(*args
)
215 class IOInterface(Interface
):
217 def ifacefmtoutenfn(self
, name
):
218 return "cell{0}_mux_outen"
220 def ifacefmtoutfn(self
, name
):
221 """ for now strip off io{0}_ part """
222 return "cell{0}_mux_out"
224 def ifacefmtinfn(self
, name
):
225 return "cell{0}_mux_in"
227 def wirefmt(self
, *args
):
228 return generic_io
.format(*args
)
231 class Interfaces(UserDict
):
232 """ contains a list of interface definitions
235 def __init__(self
, pth
=None):
238 UserDict
.__init
__(self
, {})
241 ift
= 'interfaces.txt'
243 ift
= os
.path
.join(pth
, ift
)
244 with
open(ift
, 'r') as ifile
:
245 for ln
in ifile
.readlines():
250 spec
, ganged
= self
.read_spec(pth
, name
)
251 iface
= Interface(name
, spec
, ganged
, count
== 1)
252 self
.ifaceadd(name
, count
, iface
)
254 def getifacetype(self
, fname
):
255 # finds the interface type, e.g sd_d0 returns "inout"
256 for iface
in self
.values():
257 typ
= iface
.getifacetype(fname
)
262 def ifaceadd(self
, name
, count
, iface
, at
=None):
264 at
= len(self
.ifacecount
)
265 self
.ifacecount
.insert(at
, (name
, count
))
268 def read_spec(self
, pth
, name
):
271 fname
= '%s.txt' % name
273 ift
= os
.path
.join(pth
, fname
)
274 with
open(ift
, 'r') as sfile
:
275 for ln
in sfile
.readlines():
282 elif ln
[1] == 'inout':
286 if bus
not in ganged
:
288 ganged
[bus
].append(name
)
292 def ifacedef(self
, f
, *args
):
293 for (name
, count
) in self
.ifacecount
:
294 for i
in range(count
):
295 f
.write(self
.data
[name
].ifacedef(i
))
297 def busfmt(self
, f
, *args
):
298 f
.write("import BUtils::*;\n\n")
299 for (name
, count
) in self
.ifacecount
:
300 for i
in range(count
):
301 bf
= self
.data
[name
].busfmt(i
)
304 def ifacefmt(self
, f
, *args
):
306 // interface declaration between %s-{0} and pinmux'''
307 for (name
, count
) in self
.ifacecount
:
308 for i
in range(count
):
309 c
= comment
% name
.upper()
311 f
.write(self
.data
[name
].ifacefmt(i
))
313 def wirefmt(self
, f
, *args
):
314 comment
= '\n // following wires capture signals ' \
315 'to IO CELL if %s-{0} is\n' \
317 for (name
, count
) in self
.ifacecount
:
318 for i
in range(count
):
321 f
.write(self
.data
[name
].wirefmt(i
))
324 # ========= Interface declarations ================ #
326 mux_interface
= MuxInterface('cell', [{'name': 'mux', 'ready': False,
328 'bitspec': '{1}', 'action': True}])
330 io_interface
= IOInterface(
332 [{'name': 'cell_out', 'enabled': True, },
333 {'name': 'cell_outen', 'enabled': True, 'outenmode': True, },
334 {'name': 'cell_in', 'action': True, 'io': True}, ])
336 # == Peripheral Interface definitions == #
337 # these are the interface of the peripherals to the pin mux
338 # Outputs from the peripherals will be inputs to the pinmux
339 # module. Hence the change in direction for most pins
341 # ======================================= #
344 if __name__
== '__main__':
346 uartinterface_decl
= Interface('uart',
348 {'name': 'tx', 'action': True},
351 twiinterface_decl
= Interface('twi',
352 [{'name': 'sda', 'outen': True},
353 {'name': 'scl', 'outen': True},
356 def _pinmunge(p
, sep
, repl
, dedupe
=True):
357 """ munges the text so it's easier to compare.
358 splits by separator, strips out blanks, re-joins.
363 p
= filter(lambda x
: x
, p
) # filter out blanks
367 """ munges the text so it's easier to compare.
369 # first join lines by semicolons, strip out returns
371 p
= map(lambda x
: x
.replace('\n', ''), p
)
373 # now split first by brackets, then spaces (deduping on spaces)
374 p
= _pinmunge(p
, "(", " ( ", False)
375 p
= _pinmunge(p
, ")", " ) ", False)
376 p
= _pinmunge(p
, " ", " ")
382 for p1
, p2
in zip(l1
, l2
):
388 ifaces
= Interfaces()
390 ifaceuart
= ifaces
['uart']
391 print (ifaceuart
.ifacedef(0))
392 print (uartinterface_decl
.ifacedef(0))
393 assert ifaceuart
.ifacedef(0) == uartinterface_decl
.ifacedef(0)
395 ifacetwi
= ifaces
['twi']
396 print (ifacetwi
.ifacedef(0))
397 print (twiinterface_decl
.ifacedef(0))
398 assert ifacetwi
.ifacedef(0) == twiinterface_decl
.ifacedef(0)