4 from UserDict
import UserDict
6 from collections
import UserDict
8 from bsv
.wire_def
import generic_io
# special case
9 from bsv
.wire_def
import muxwire
# special case
10 from ifacebase
import InterfacesBase
11 from bsv
.peripheral_gen
import PeripheralIface
12 from bsv
.peripheral_gen
import PeripheralInterfaces
16 """ pin interface declaration.
17 * name is the name of the pin
18 * ready, enabled and io all create a (* .... *) prefix
19 * action changes it to an "in" if true
22 def __init__(self
, name
,
35 self
.enabled
= enabled
38 self
.bitspec
= bitspec
if bitspec
else 'Bit#(1)'
39 self
.outenmode
= outenmode
41 # bsv will look like this (method declaration):
43 (*always_ready,always_enabled*) method Bit#(1) io0_cell_outen;
44 (*always_ready,always_enabled,result="io"*) method
45 Action io0_inputval (Bit#(1) in);
48 def ifacepfmt(self
, fmtfn
):
52 name
= fmtfn(self
.name_
)
57 res
+= "#(%s) %s;" % (self
.bitspec
, name
)
60 def ifacefmt(self
, fmtfn
):
64 status
.append('always_ready')
66 status
.append('always_enabled')
68 status
.append('result="io"')
71 res
+= ','.join(status
)
76 name
= fmtfn(self
.name
)
80 res
+= ' (%s in)' % self
.bitspec
82 res
+= " %s " % self
.bitspec
87 def ifacedef(self
, fmtoutfn
, fmtinfn
, fmtdecfn
):
90 fmtname
= fmtinfn(self
.name
)
92 res
+= fmtdecfn(self
.name
)
93 res
+= '(%s in);\n' % self
.bitspec
94 res
+= ' %s<=in;\n' % fmtname
97 fmtname
= fmtoutfn(self
.name
)
98 res
+= "%s=%s;" % (self
.name
, fmtname
)
100 # sample bsv method definition :
102 method Action cell0_mux(Bit#(2) in);
107 # sample bsv wire (wire definiton):
109 Wire#(Bit#(2)) wrcell0_mux<-mkDWire(0);
112 def wirefmt(self
, fmtoutfn
, fmtinfn
, fmtdecfn
):
113 res
= ' Wire#(%s) ' % self
.bitspec
115 res
+= '%s' % fmtinfn(self
.name
)
117 res
+= '%s' % fmtoutfn(self
.name
)
118 res
+= "<-mkDWire(0);"
121 def ifacedef2(self
, fmtoutfn
, fmtinfn
, fmtdecfn
):
123 fmtname
= fmtinfn(self
.name
)
124 res
= " interface %s = interface Put\n" % self
.name_
127 #res += fmtdecfn(self.name)
128 res
+= '(%s in);\n' % self
.bitspec
129 res
+= ' %s<=in;\n' % fmtname
130 res
+= ' endmethod\n'
131 res
+= ' endinterface;'
133 fmtname
= fmtoutfn(self
.name
)
134 res
= " interface %s = interface Get\n" % self
.name_
135 res
+= ' method ActionValue#'
136 res
+= '(%s) get;\n' % self
.bitspec
137 res
+= " return %s;\n" % (fmtname
)
138 res
+= ' endmethod\n'
139 res
+= ' endinterface;'
142 def ifacedef3(self
, idx
, fmtoutfn
, fmtinfn
, fmtdecfn
):
144 fmtname
= fmtinfn(self
.name
)
145 if self
.name
.endswith('outen'):
149 res
= " %s <= in[%d];" % (fmtname
, idx
)
151 fmtname
= fmtoutfn(self
.name
)
152 res
= " tget[%d] = %s;" % (idx
, fmtname
)
157 class Interface(PeripheralIface
):
158 """ create an interface from a list of pinspecs.
159 each pinspec is a dictionary, see Pin class arguments
160 single indicates that there is only one of these, and
161 so the name must *not* be extended numerically (see pname)
163 # sample interface object:
165 twiinterface_decl = Interface('twi',
166 [{'name': 'sda', 'outen': True},
167 {'name': 'scl', 'outen': True},
171 def __init__(self
, ifacename
, pinspecs
, ganged
=None, single
=False):
172 PeripheralIface
.__init
__(self
, ifacename
)
173 self
.ifacename
= ifacename
174 self
.ganged
= ganged
or {}
175 self
.pins
= [] # a list of instances of class Pin
176 self
.pinspecs
= pinspecs
# a list of dictionary
179 for idx
, p
in enumerate(pinspecs
):
184 if p
.get('outen') is True: # special case, generate 3 pins
186 for psuffix
in ['out', 'outen', 'in']:
187 # changing the name (like sda) to (twi_sda_out)
188 _p
['name_'] = "%s_%s" % (p
['name'], psuffix
)
189 _p
['name'] = "%s_%s" % (self
.pname(p
['name']), psuffix
)
190 _p
['action'] = psuffix
!= 'in'
192 self
.pins
.append(Pin(**_p
))
193 # will look like {'name': 'twi_sda_out', 'action': True}
194 # {'name': 'twi_sda_outen', 'action': True}
195 #{'name': 'twi_sda_in', 'action': False}
196 # NOTice - outen key is removed
199 if name
.isdigit(): # HACK! deals with EINT case
200 name
= self
.pname(name
)
203 _p
['name'] = self
.pname(p
['name'])
204 self
.pins
.append(Pin(**_p
))
206 # sample interface object:
208 uartinterface_decl = Interface('uart',
210 {'name': 'tx', 'action': True},
214 getifacetype is called multiple times in actual_pinmux.py
215 x = ifaces.getifacetype(temp), where temp is uart_rx, spi_mosi
216 Purpose is to identify is function : input/output/inout
219 def getifacetype(self
, name
):
220 for p
in self
.pinspecs
:
221 fname
= "%s_%s" % (self
.ifacename
, p
['name'])
222 # print "search", self.ifacename, name, fname
232 """ generates the interface spec e.g. flexbus_ale
233 if there is only one flexbus interface, or
234 sd{0}_cmd if there are several. string format
235 function turns this into sd0_cmd, sd1_cmd as
236 appropriate. single mode stops the numerical extension.
239 return self
.ifacename
240 return '%s{0}' % self
.ifacename
242 def pname(self
, name
):
243 """ generates the interface spec e.g. flexbus_ale
244 if there is only one flexbus interface, or
245 sd{0}_cmd if there are several. string format
246 function turns this into sd0_cmd, sd1_cmd as
247 appropriate. single mode stops the numerical extension.
249 return "%s_%s" % (self
.iname(), name
)
251 def busfmt(self
, *args
):
252 """ this function creates a bus "ganging" system based
253 on input from the {interfacename}.txt file.
254 only inout pins that are under the control of the
255 interface may be "ganged" together.
258 return '' # when self.ganged is None
261 for (k
, pnames
) in self
.ganged
.items():
262 name
= self
.pname('%senable' % k
).format(*args
)
263 decl
= 'Bit#(1) %s = 0;' % name
266 for p
in self
.pinspecs
:
267 if p
['name'] not in pnames
:
269 pname
= self
.pname(p
['name']).format(*args
)
270 if p
.get('outen') is True:
271 outname
= self
.ifacefmtoutfn(pname
)
272 ganged
.append("%s_outen" % outname
) # match wirefmt
274 gangedfmt
= '{%s} = duplicate(%s);'
275 res
.append(gangedfmt
% (',\n '.join(ganged
), name
))
276 return '\n'.join(res
) + '\n\n'
278 def wirefmt(self
, *args
):
279 res
= '\n'.join(map(self
.wirefmtpin
, self
.pins
)).format(*args
)
283 def ifacepfmt(self
, *args
):
284 res
= '\n'.join(map(self
.ifacepfmtdecpin
, self
.pins
)).format(*args
)
285 return '\n' + res
# pins is a list
287 def ifacefmt(self
, *args
):
288 res
= '\n'.join(map(self
.ifacefmtdecpin
, self
.pins
)).format(*args
)
289 return '\n' + res
# pins is a list
291 def ifacepfmtdecfn(self
, name
):
294 def ifacefmtdecfn(self
, name
):
295 return name
# like: uart
297 def ifacefmtdecfn2(self
, name
):
298 return name
# like: uart
300 def ifacefmtdecfn3(self
, name
):
302 return "%s_outen" % name
# like uart_outen
304 def ifacefmtoutfn(self
, name
):
305 return "wr%s" % name
# like wruart
307 def ifacefmtinfn(self
, name
):
310 def wirefmtpin(self
, pin
):
311 return pin
.wirefmt(self
.ifacefmtoutfn
, self
.ifacefmtinfn
,
314 def ifacepfmtdecpin(self
, pin
):
315 return pin
.ifacepfmt(self
.ifacepfmtdecfn
)
317 def ifacefmtdecpin(self
, pin
):
318 return pin
.ifacefmt(self
.ifacefmtdecfn
)
320 def ifacefmtpin(self
, pin
):
321 decfn
= self
.ifacefmtdecfn2
322 outfn
= self
.ifacefmtoutfn
323 # print pin, pin.outenmode
325 decfn
= self
.ifacefmtdecfn3
326 outfn
= self
.ifacefmtoutenfn
327 return pin
.ifacedef(outfn
, self
.ifacefmtinfn
,
330 def ifacedef2pin(self
, pin
):
331 decfn
= self
.ifacefmtdecfn2
332 outfn
= self
.ifacefmtoutfn
333 # print pin, pin.outenmode
335 decfn
= self
.ifacefmtdecfn3
336 outfn
= self
.ifacefmtoutenfn
337 return pin
.ifacedef2(outfn
, self
.ifacefmtinfn
,
340 def ifacedef(self
, *args
):
341 res
= '\n'.join(map(self
.ifacefmtpin
, self
.pins
))
342 res
= res
.format(*args
)
343 return '\n' + res
+ '\n'
345 def ifacedef2(self
, *args
):
346 res
= '\n'.join(map(self
.ifacedef2pin
, self
.pins
))
347 res
= res
.format(*args
)
348 return '\n' + res
+ '\n'
350 def vectorifacedef2(self
, pins
, count
, names
, bitfmt
, *args
):
354 # XXX HACK! assume in, out and inout, create set of indices
355 # that are repeated three times.
357 # ARG even worse hack for LCD *sigh*...
358 if names
[1] is None and names
[2] is None:
359 plens
= range(len(pins
))
361 for i
in range(0, len(pins
), 3):
362 plens
+= [i
/3, i
/3, i
/3]
363 for (typ
, txt
) in map(self
.ifacedef3pin
, plens
, pins
):
368 elif typ
== 'tputen':
370 tput
= '\n'.join(tput
).format(*args
)
371 tget
= '\n'.join(tget
).format(*args
)
372 tputen
= '\n'.join(tputen
).format(*args
)
373 bitfmt
= bitfmt
.format(count
)
375 interface {3} = interface Put#({0})
376 method Action put({2} in);
382 interface {3} = interface Put#({0})
383 method Action put({2} in);
389 interface {3} = interface Get#({0})
390 method ActionValue#({2}) get;
398 tlist
= [tput
, tputen
, tget
]
399 for i
, n
in enumerate(names
):
401 res
+= template
[i
].format(count
, tlist
[i
], bitfmt
, n
)
402 return '\n' + res
+ '\n'
405 class MuxInterface(Interface
):
407 def wirefmt(self
, *args
):
408 return muxwire
.format(*args
)
411 class IOInterface(Interface
):
413 def ifacefmtoutenfn(self
, name
):
414 return "cell{0}_mux_outen"
416 def ifacefmtoutfn(self
, name
):
417 """ for now strip off io{0}_ part """
418 return "cell{0}_mux_out"
420 def ifacefmtinfn(self
, name
):
421 return "cell{0}_mux_in"
423 def wirefmt(self
, *args
):
424 return generic_io
.format(*args
)
427 class InterfaceBus(object):
429 def __init__(self
, namelist
, bitspec
, filterbus
):
430 self
.namelist
= namelist
431 self
.bitspec
= bitspec
432 self
.fbus
= filterbus
# filter identifying which are bus pins
434 def get_nonbuspins(self
):
435 return filter(lambda x
: not x
.name_
.startswith(self
.fbus
), self
.pins
)
437 def get_buspins(self
):
438 return filter(lambda x
: x
.name_
.startswith(self
.fbus
), self
.pins
)
440 def ifacepfmt(self
, *args
):
441 pins
= self
.get_nonbuspins()
442 res
= '\n'.join(map(self
.ifacepfmtdecpin
, pins
)).format(*args
)
443 res
= res
.format(*args
)
445 pins
= self
.get_buspins()
446 plen
= self
.get_n_iopins(pins
)
449 template
= " interface {1}#(%s) {2};\n" % self
.bitspec
450 for i
, n
in enumerate(self
.namelist
):
453 ftype
= 'Get' if i
== 2 else "Put"
454 res
+= template
.format(plen
, ftype
, n
)
458 def ifacedef2(self
, *args
):
459 pins
= self
.get_nonbuspins()
460 res
= '\n'.join(map(self
.ifacedef2pin
, pins
))
461 res
= res
.format(*args
)
463 pins
= self
.get_buspins()
464 plen
= self
.get_n_iopins(pins
)
465 bitspec
= self
.bitspec
.format(plen
)
466 return '\n' + res
+ self
.vectorifacedef2(pins
, plen
,
467 self
.namelist
, bitspec
, *args
) + '\n'
469 def ifacedef3pin(self
, idx
, pin
):
470 decfn
= self
.ifacefmtdecfn2
471 outfn
= self
.ifacefmtoutfn
472 # print pin, pin.outenmode
474 decfn
= self
.ifacefmtdecfn3
475 outfn
= self
.ifacefmtoutenfn
476 return pin
.ifacedef3(idx
, outfn
, self
.ifacefmtinfn
,
480 class InterfaceLCD(InterfaceBus
, Interface
):
482 def __init__(self
, *args
):
483 InterfaceBus
.__init
__(self
, ['data_out', None, None],
485 Interface
.__init
__(self
, *args
)
487 def get_n_iopins(self
, pins
): # HACK! assume in/out/outen so div by 3
491 class InterfaceNSPI(InterfaceBus
, Interface
):
493 def __init__(self
, *args
):
494 InterfaceBus
.__init
__(self
, ['io_out', 'io_out_en', 'io_in'],
496 Interface
.__init
__(self
, *args
)
498 def get_n_iopins(self
, pins
): # HACK! assume in/out/outen so div by 3
502 class InterfaceEINT(Interface
):
503 """ uses old-style (non-get/put) for now
505 def ifacepfmt(self
, *args
):
506 res
= '\n'.join(map(self
.ifacefmtdecpin
, self
.pins
)).format(*args
)
507 return '\n' + res
# pins is a list
509 def ifacedef2(self
, *args
):
510 return self
.ifacedef(*args
)
514 class InterfaceGPIO(InterfaceBus
, Interface
):
516 def __init__(self
, ifacename
, pinspecs
, ganged
=None, single
=False):
517 InterfaceBus
.__init
__(self
, ['out', 'out_en', 'in'],
518 "Vector#({0},Bit#(1))", ifacename
[-1])
519 Interface
.__init
__(self
, ifacename
, pinspecs
, ganged
, single
)
521 def get_n_iopins(self
, pins
): # HACK! assume in/out/outen so div by 3
525 class Interfaces(InterfacesBase
, PeripheralInterfaces
):
526 """ contains a list of interface definitions
529 def __init__(self
, pth
=None):
530 InterfacesBase
.__init
__(self
, Interface
, pth
,
531 {'gpio': InterfaceGPIO
,
532 'spi': InterfaceNSPI
,
534 'qspi': InterfaceNSPI
,
535 'eint': InterfaceEINT
})
536 PeripheralInterfaces
.__init
__(self
)
538 def ifacedef(self
, f
, *args
):
539 for (name
, count
) in self
.ifacecount
:
540 for i
in range(count
):
541 f
.write(self
.data
[name
].ifacedef(i
))
543 def ifacedef2(self
, f
, *args
):
544 c
= " interface {0} = interface PeripheralSide{1}"
545 for (name
, count
) in self
.ifacecount
:
546 for i
in range(count
):
547 iname
= self
.data
[name
].iname().format(i
)
548 f
.write(c
.format(iname
, name
.upper()))
549 f
.write(self
.data
[name
].ifacedef2(i
))
550 f
.write(" endinterface;\n\n")
552 def busfmt(self
, f
, *args
):
553 f
.write("import BUtils::*;\n\n")
554 for (name
, count
) in self
.ifacecount
:
555 for i
in range(count
):
556 bf
= self
.data
[name
].busfmt(i
)
559 def ifacepfmt(self
, f
, *args
):
561 // interface declaration between {0} and pinmux
562 (*always_ready,always_enabled*)
563 interface PeripheralSide{0};'''
564 for (name
, count
) in self
.ifacecount
:
565 f
.write(comment
.format(name
.upper()))
566 f
.write(self
.data
[name
].ifacepfmt(0))
567 f
.write("\n endinterface\n")
569 def ifacefmt(self
, f
, *args
):
571 // interface declaration between %s-{0} and pinmux'''
572 for (name
, count
) in self
.ifacecount
:
573 for i
in range(count
):
574 c
= comment
% name
.upper()
576 f
.write(self
.data
[name
].ifacefmt(i
))
578 def ifacefmt2(self
, f
, *args
):
580 interface PeripheralSide{0} {1};'''
581 for (name
, count
) in self
.ifacecount
:
582 for i
in range(count
):
583 iname
= self
.data
[name
].iname().format(i
)
584 f
.write(comment
.format(name
.upper(), iname
))
586 def wirefmt(self
, f
, *args
):
587 comment
= '\n // following wires capture signals ' \
588 'to IO CELL if %s-{0} is\n' \
590 for (name
, count
) in self
.ifacecount
:
591 for i
in range(count
):
594 f
.write(self
.data
[name
].wirefmt(i
))
597 # ========= Interface declarations ================ #
599 mux_interface
= MuxInterface('cell',
600 [{'name': 'mux', 'ready': False, 'enabled': False,
601 'bitspec': '{1}', 'action': True}])
603 io_interface
= IOInterface(
605 [{'name': 'cell_out', 'enabled': True, },
606 {'name': 'cell_outen', 'enabled': True, 'outenmode': True, },
607 {'name': 'cell_in', 'action': True, 'io': True}, ])
609 # == Peripheral Interface definitions == #
610 # these are the interface of the peripherals to the pin mux
611 # Outputs from the peripherals will be inputs to the pinmux
612 # module. Hence the change in direction for most pins
614 # ======================================= #
617 if __name__
== '__main__':
619 uartinterface_decl
= Interface('uart',
621 {'name': 'tx', 'action': True},
624 twiinterface_decl
= Interface('twi',
625 [{'name': 'sda', 'outen': True},
626 {'name': 'scl', 'outen': True},
629 def _pinmunge(p
, sep
, repl
, dedupe
=True):
630 """ munges the text so it's easier to compare.
631 splits by separator, strips out blanks, re-joins.
636 p
= filter(lambda x
: x
, p
) # filter out blanks
640 """ munges the text so it's easier to compare.
642 # first join lines by semicolons, strip out returns
644 p
= map(lambda x
: x
.replace('\n', ''), p
)
646 # now split first by brackets, then spaces (deduping on spaces)
647 p
= _pinmunge(p
, "(", " ( ", False)
648 p
= _pinmunge(p
, ")", " ) ", False)
649 p
= _pinmunge(p
, " ", " ")
655 for p1
, p2
in zip(l1
, l2
):
661 ifaces
= Interfaces()
663 ifaceuart
= ifaces
['uart']
664 print (ifaceuart
.ifacedef(0))
665 print (uartinterface_decl
.ifacedef(0))
666 assert ifaceuart
.ifacedef(0) == uartinterface_decl
.ifacedef(0)
668 ifacetwi
= ifaces
['twi']
669 print (ifacetwi
.ifacedef(0))
670 print (twiinterface_decl
.ifacedef(0))
671 assert ifacetwi
.ifacedef(0) == twiinterface_decl
.ifacedef(0)